forked from OSchip/llvm-project
Revert "[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction"
This reverts commits r347532. Forget add the option -mtriple powerpc64-unknown-linux-gnu. So other platform is error except for PowerPC. llvm-svn: 347534
This commit is contained in:
Kang Zhang
parent
b7a50e5796
commit
840e98f9f1
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@ -2984,10 +2984,8 @@ bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
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if (PostRA) {
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if (isVFReg(MI.getOperand(0).getReg()))
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III.ImmOpcode = PPC::LXSSP;
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else {
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else
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III.ImmOpcode = PPC::LFS;
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III.ImmMustBeMultipleOf = 1;
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}
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break;
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}
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LLVM_FALLTHROUGH;
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@ -2998,10 +2996,8 @@ bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
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if (PostRA) {
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if (isVFReg(MI.getOperand(0).getReg()))
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III.ImmOpcode = PPC::LXSD;
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else {
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else
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III.ImmOpcode = PPC::LFD;
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III.ImmMustBeMultipleOf = 1;
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}
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break;
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}
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LLVM_FALLTHROUGH;
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@ -3016,10 +3012,8 @@ bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
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if (PostRA) {
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if (isVFReg(MI.getOperand(0).getReg()))
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III.ImmOpcode = PPC::STXSSP;
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else {
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else
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III.ImmOpcode = PPC::STFS;
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III.ImmMustBeMultipleOf = 1;
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}
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break;
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}
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LLVM_FALLTHROUGH;
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@ -3030,10 +3024,8 @@ bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
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if (PostRA) {
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if (isVFReg(MI.getOperand(0).getReg()))
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III.ImmOpcode = PPC::STXSD;
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else {
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else
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III.ImmOpcode = PPC::STFD;
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III.ImmMustBeMultipleOf = 1;
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}
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break;
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}
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LLVM_FALLTHROUGH;
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@ -1,161 +0,0 @@
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# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole -mcpu=pwr9 %s -o - | FileCheck %s
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---
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name: testLXSSPX
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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- { id: 5, class: g8rc, preferred-register: '' }
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- { id: 6, class: g8rc, preferred-register: '' }
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- { id: 7, class: vssrc, preferred-register: '' }
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- { id: 8, class: gprc, preferred-register: '' }
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- { id: 9, class: g8rc, preferred-register: '' }
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- { id: 10, class: g8rc, preferred-register: '' }
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- { id: 11, class: g8rc, preferred-register: '' }
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- { id: 12, class: vssrc, preferred-register: '' }
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- { id: 13, class: vssrc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1 = COPY $x4
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%0 = COPY $x3
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%2 = COPY %1.sub_32
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%3 = ADDI %2, 1
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%5 = IMPLICIT_DEF
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%4 = INSERT_SUBREG %5, killed %3, 1
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%6 = LI8 97
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%7 = LXSSPX %0, killed %6, implicit $rm
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; CHECK: lfs [[REG1:[0-9]+]], 97(3)
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%8 = ADDI %2, 2
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%10 = IMPLICIT_DEF
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%9 = INSERT_SUBREG %10, killed %8, 1
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%11 = LI8 -92
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%12 = LXSSPX %0, killed %11, implicit $rm
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; CHECK-NEXT: lfs [[REG2:[0-9]+]], -92(3)
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%13 = XSADDSP killed %7, killed %12
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; CHECK-NEXT: xsaddsp {{[0-9]+}}, [[REG1]], [[REG2]]
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$f1 = COPY %13
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BLR8 implicit $lr8, implicit $rm, implicit $f1
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...
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---
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name: testLXSDX
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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- { id: 5, class: g8rc, preferred-register: '' }
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- { id: 6, class: g8rc, preferred-register: '' }
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- { id: 7, class: vsfrc, preferred-register: '' }
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- { id: 8, class: gprc, preferred-register: '' }
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- { id: 9, class: g8rc, preferred-register: '' }
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- { id: 10, class: g8rc, preferred-register: '' }
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- { id: 11, class: g8rc, preferred-register: '' }
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- { id: 12, class: vsfrc, preferred-register: '' }
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- { id: 13, class: vsfrc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1 = COPY $x4
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%0 = COPY $x3
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%2 = COPY %1.sub_32
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%3 = ADDI %2, 1
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%5 = IMPLICIT_DEF
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%4 = INSERT_SUBREG %5, killed %3, 1
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%6 = LI8 99
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%7 = LXSDX %0, killed %6, implicit $rm
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; CHECK: lfd [[REG1:[0-9]+]], 99(3)
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%8 = ADDI %2, 2
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%10 = IMPLICIT_DEF
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%9 = INSERT_SUBREG %10, killed %8, 1
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%11 = LI8 -120
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%12 = LXSDX %0, killed %11, implicit $rm
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; CHECK-NEXT: lfd [[REG2:[0-9]+]], -120(3)
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%13 = XSADDDP killed %7, killed %12, implicit $rm
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; CHECK-NEXT: xsadddp {{[0-9]+}}, [[REG1]], [[REG2]]
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$f1 = COPY %13
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BLR8 implicit $lr8, implicit $rm, implicit $f1
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...
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---
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name: testSTXSSPX
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: vssrc, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$f1', virtual-reg: '%1' }
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- { reg: '$x5', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x3, $f1, $x5
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%2 = COPY $x5
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%1 = COPY $f1
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%0 = COPY $x3
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%3 = LI8 443
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STXSSPX %1, %0, killed %3, implicit $rm
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; CHECK: stfs {{[0-9]+}}, 443(3)
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BLR8 implicit $lr8, implicit $rm
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...
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---
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name: testSTXSDX
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: vsfrc, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$f1', virtual-reg: '%1' }
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- { reg: '$x5', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x3, $f1, $x5
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%2 = COPY $x5
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%1 = COPY $f1
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%0 = COPY $x3
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%3 = LI8 7
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STXSDX %1, %0, killed %3, implicit $rm
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; CHECK: stfd {{[0-9]+}}, 7(3)
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BLR8 implicit $lr8, implicit $rm
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...
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