forked from OSchip/llvm-project
[M68k] Tidy up some bit shifting during code emission
This fixes some issues with bit masking when emitting instructions (including one TODO). Differential Revision: https://reviews.llvm.org/D98527
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@ -162,13 +162,13 @@ unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
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unsigned Written = 0;
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if (Reg) {
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uint32_t Val = RI->getEncodingValue(RegNum);
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Buffer |= Val << Offset;
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Buffer |= (Val & 7) << Offset;
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Offset += 3;
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Written += 3;
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}
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if (DA) {
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Buffer |= (char)M68kII::isAddressRegister(RegNum) << Offset;
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Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
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Written++;
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}
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@ -179,13 +179,9 @@ static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad,
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uint64_t &Buffer, unsigned Offset) {
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assert(Size + Offset <= 64 && isUIntN(Size, Val) && "Value does not fit");
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// Pad the instruction with zeros if any
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// FIXME Emit zeros in the padding, since there might be trash in the buffer.
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Size += Pad;
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// Writing Value in host's endianness
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Buffer |= Val << Offset;
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return Size;
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Buffer |= (Val & ((1ULL << Size) - 1)) << Offset;
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return Size + Pad;
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}
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unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
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@ -316,8 +312,7 @@ unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
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return Size;
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}
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return EmitConstant(Imm & (UINT64_MAX >> (64 - Size)), Size, Pad, Buffer,
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Offset);
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return EmitConstant(Imm & ((1ULL << Size) - 1), Size, Pad, Buffer, Offset);
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}
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#include "M68kGenMCCodeBeads.inc"
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