forked from OSchip/llvm-project
ARM: add correct kill flags when combining stm instructions
When the store sequence being combined actually stores the base register, we should not mark it as killed until the end. rdar://21504262 llvm-svn: 241003
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@ -743,6 +743,12 @@ void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
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}
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}
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for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
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MachineOperand &TransferOp = memOps[i].MBBI->getOperand(0);
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if (TransferOp.isUse() && TransferOp.getReg() == Base)
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BaseKill = false;
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}
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SmallVector<std::pair<unsigned, bool>, 8> Regs;
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SmallVector<unsigned, 8> ImpDefs;
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SmallVector<MachineOperand *, 8> UsesOfImpDefs;
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@ -0,0 +1,43 @@
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; RUN: llc -mtriple=thumbv7-apple-ios7.0 -o - %s -verify-machineinstrs | FileCheck %s
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; The base register for the store is killed by the last instruction, but is
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; actually also used during as part of the store itself. If an extra ADD is
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; inserted, it should not kill the base.
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define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) {
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; CHECK-LABEL: test_base_kill:
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; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4
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; CHECK: stm.w [[NEWBASE]], {r0, r1, r2}
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%addr.1 = getelementptr i32, i32* %addr, i32 1
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store i32 %v0, i32* %addr.1
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%addr.2 = getelementptr i32, i32* %addr, i32 2
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store i32 %v1, i32* %addr.2
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%addr.3 = getelementptr i32, i32* %addr, i32 3
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%val = ptrtoint i32* %addr to i32
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store i32 %val, i32* %addr.3
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ret void
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}
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; Similar, but it's not sufficient to look at just the last instruction (where
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; liveness of the base is determined). An intervening instruction might be moved
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; past it to form the STM.
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define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) {
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; CHECK-LABEL: test_base_kill_mid:
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; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4
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; CHECK: stm.w [[NEWBASE]], {r0, r1, r2}
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%addr.1 = getelementptr i32, i32* %addr, i32 1
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store i32 %v0, i32* %addr.1
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%addr.2 = getelementptr i32, i32* %addr, i32 2
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%val = ptrtoint i32* %addr to i32
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store i32 %val, i32* %addr.2
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%addr.3 = getelementptr i32, i32* %addr, i32 3
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store i32 %v1, i32* %addr.3
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ret void
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}
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