From 83e76327e8308073690cd7a8b6caab56cdbe49e5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sat, 27 Feb 2016 12:51:46 +0000 Subject: [PATCH] [X86][AVX] vpermilvar.pd mask element indices only use bit1 llvm-svn: 262134 --- .../test/CodeGen/X86/vector-shuffle-combining-avx.ll | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll index 72b85f0be98c..758f2becbe64 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll @@ -46,24 +46,24 @@ define <8 x float> @combine_vpermilvar_8f32(<8 x float> %a0) { define <2 x double> @combine_vpermilvar_2f64(<2 x double> %a0) { ; ALL-LABEL: combine_vpermilvar_2f64: ; ALL: # BB#0: -; ALL-NEXT: movl $1, %eax +; ALL-NEXT: movl $2, %eax ; ALL-NEXT: vmovq %rax, %xmm1 ; ALL-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 ; ALL-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 ; ALL-NEXT: retq - %1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> ) - %2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %1, <2 x i64> ) + %1 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> ) + %2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %1, <2 x i64> ) ret <2 x double> %2 } define <4 x double> @combine_vpermilvar_4f64(<4 x double> %a0) { ; ALL-LABEL: combine_vpermilvar_4f64: ; ALL: # BB#0: -; ALL-NEXT: vmovapd {{.*#+}} ymm1 = [1,0,1,0] +; ALL-NEXT: vmovapd {{.*#+}} ymm1 = [2,0,2,0] ; ALL-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 ; ALL-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 ; ALL-NEXT: retq - %1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> ) - %2 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %1, <4 x i64> ) + %1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> ) + %2 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %1, <4 x i64> ) ret <4 x double> %2 }