From 83b67526d5c2ba070996697e73e8954776986303 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 22 Jan 2020 16:30:35 +0100 Subject: [PATCH] [VE] select and selectcc patterns Summary: select and selectcc isel patterns and tests for i32/i64 and fp32/fp64. Includes optimized selectcc patterns for fmin/fmax/maxs/mins. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73195 --- llvm/lib/Target/VE/VEInstrInfo.td | 220 ++++++++++++++++++++++++ llvm/test/CodeGen/VE/max.ll | 199 ++++++++++++++++++++++ llvm/test/CodeGen/VE/min.ll | 199 ++++++++++++++++++++++ llvm/test/CodeGen/VE/select.ll | 57 +++++++ llvm/test/CodeGen/VE/selectccf32.ll | 217 ++++++++++++++++++++++++ llvm/test/CodeGen/VE/selectccf32c.ll | 116 +++++++++++++ llvm/test/CodeGen/VE/selectccf32i.ll | 241 +++++++++++++++++++++++++++ llvm/test/CodeGen/VE/selectccf64.ll | 189 +++++++++++++++++++++ llvm/test/CodeGen/VE/selectccf64c.ll | 102 ++++++++++++ llvm/test/CodeGen/VE/selectccf64i.ll | 201 ++++++++++++++++++++++ llvm/test/CodeGen/VE/selectcci32.ll | 197 ++++++++++++++++++++++ llvm/test/CodeGen/VE/selectcci32c.ll | 116 +++++++++++++ llvm/test/CodeGen/VE/selectcci32i.ll | 211 +++++++++++++++++++++++ llvm/test/CodeGen/VE/selectcci64.ll | 169 +++++++++++++++++++ llvm/test/CodeGen/VE/selectcci64c.ll | 102 ++++++++++++ llvm/test/CodeGen/VE/selectcci64i.ll | 183 ++++++++++++++++++++ 16 files changed, 2719 insertions(+) create mode 100644 llvm/test/CodeGen/VE/max.ll create mode 100644 llvm/test/CodeGen/VE/min.ll create mode 100644 llvm/test/CodeGen/VE/select.ll create mode 100644 llvm/test/CodeGen/VE/selectccf32.ll create mode 100644 llvm/test/CodeGen/VE/selectccf32c.ll create mode 100644 llvm/test/CodeGen/VE/selectccf32i.ll create mode 100644 llvm/test/CodeGen/VE/selectccf64.ll create mode 100644 llvm/test/CodeGen/VE/selectccf64c.ll create mode 100644 llvm/test/CodeGen/VE/selectccf64i.ll create mode 100644 llvm/test/CodeGen/VE/selectcci32.ll create mode 100644 llvm/test/CodeGen/VE/selectcci32c.ll create mode 100644 llvm/test/CodeGen/VE/selectcci32i.ll create mode 100644 llvm/test/CodeGen/VE/selectcci64.ll create mode 100644 llvm/test/CodeGen/VE/selectcci64c.ll create mode 100644 llvm/test/CodeGen/VE/selectcci64i.ll diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 9fb0a866f326..7bfb50098f46 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -368,6 +368,13 @@ multiclass RRImopc, SDNode OpNode, let Constraints = "$sx = $sd", DisableEncoding = "$sd" in multiclass RRCMOVmopc, RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { + def rr : RR< + opc, (outs I64:$sx), (ins CCOp:$cf, RC:$sy, I64:$sz, I64:$sd), + !strconcat(opcStr, " $sx, $sz, $sy")> { + let cy = 1; + let cz = 1; + let hasSideEffects = 0; + } def rm0 : RR< opc, (outs I64:$sx), (ins CCOp:$cf, RC:$sy, immOp2:$sz, I64:$sd), !strconcat(opcStr, " $sx, (${sz})0, $sy")> { @@ -449,6 +456,19 @@ defm CPSU : RRNDm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>; let cx = 0 in defm CPX : RRNDm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>; +// cx: sx/zx, cw: max/min + +let cw = 0 in defm CMXa : + RRNDm<"maxs.l", 0x68, I64, i64, simm7Op64, uimm6Op64>; + +let cx = 0, cw = 0 in defm CMSa : + RRNDm<"maxs.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>; + +let cw = 1 in defm CMXi : + RRNDm<"mins.l", 0x68, I64, i64, simm7Op64, uimm6Op64>; + +let cx = 1, cw = 0 in defm CMSi : + RRNDm<"mins.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>; // 5.3.2.3. Logical Arithmetic Operation Instructions @@ -481,6 +501,20 @@ defm FCP : RRNDm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>; let cx = 1 in defm FCPS : RRNDm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>; +// FCM +let cw = 0 in { + let cx = 0 in + defm FCMA : RRNDm<"fmax.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>; + let cx = 1 in + defm FCMAS : RRNDm<"fmax.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>; +} +let cw = 1 in { + let cx = 0 in + defm FCMI : RRNDm<"fmin.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>; + let cx = 1 in + defm FCMIS : RRNDm<"fmin.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>; +} + // Load and Store instructions // As 1st step, only uses sz and imm32 to represent $addr let mayLoad = 1, hasSideEffects = 0 in { @@ -676,6 +710,192 @@ def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)), 63, (ORim1 0, 0)), sub_i32)>; +// Special SELECTCC pattern matches +// Use min/max for better performance. +// +// MAX/MIN %res, %lhs, %rhs + +def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)), + (FCMArr $LHS, $RHS)>; +def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGT)), + (FCMASrr $LHS, $RHS)>; +def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGT)), + (CMXarr $LHS, $RHS)>; +def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGT)), + (CMSarr $LHS, $RHS)>; +def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGE)), + (FCMArr $LHS, $RHS)>; +def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGE)), + (FCMASrr $LHS, $RHS)>; +def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGE)), + (CMXarr $LHS, $RHS)>; +def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGE)), + (CMSarr $LHS, $RHS)>; + +def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLT)), + (FCMIrr $LHS, $RHS)>; +def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLT)), + (FCMISrr $LHS, $RHS)>; +def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLT)), + (CMXirr $LHS, $RHS)>; +def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLT)), + (CMSirr $LHS, $RHS)>; +def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLE)), + (FCMIrr $LHS, $RHS)>; +def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLE)), + (FCMISrr $LHS, $RHS)>; +def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLE)), + (CMXirr $LHS, $RHS)>; +def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLE)), + (CMSirr $LHS, $RHS)>; + +// Generic SELECTCC pattern matches +// +// CMP %tmp, %l, %r ; compare %l and %r +// or %res, %f, (0)1 ; initialize by %f +// CMOV %res, %t, %tmp ; set %t if %tmp is true + +// selectcc for i64 result +def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCSIOp:$cond)), + (CMOVWrr (icond2cc $cond), (CPSrr $l, $r), $t, $f)>; +def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCUIOp:$cond)), + (CMOVWrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; +def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCSIOp:$cond)), + (CMOVLrr (icond2cc $cond), (CPXrr $l, $r), $t, $f)>; +def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCUIOp:$cond)), + (CMOVLrr (icond2cc $cond), (CMPrr $l, $r), $t, $f)>; +def : Pat<(i64 (selectcc f32:$l, f32:$r, i64:$t, i64:$f, cond:$cond)), + (CMOVSrr (fcond2cc $cond), (FCPSrr $l, $r), $t, $f)>; +def : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)), + (CMOVDrr (fcond2cc $cond), (FCPrr $l, $r), $t, $f)>; + +// selectcc for i32 result +def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrr (icond2cc $cond), + (CPSrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; +def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrr (icond2cc $cond), + (CMPUWrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; +def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrr (icond2cc $cond), + (CPXrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; +def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrr (icond2cc $cond), + (CMPrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; +def : Pat<(i32 (selectcc f32:$l, f32:$r, i32:$t, i32:$f, cond:$cond)), + (EXTRACT_SUBREG + (CMOVSrr (fcond2cc $cond), + (FCPSrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; +def : Pat<(i32 (selectcc f64:$l, f64:$r, i32:$t, i32:$f, cond:$cond)), + (EXTRACT_SUBREG + (CMOVDrr (fcond2cc $cond), + (FCPrr $l, $r), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; + +// selectcc for f64 result +def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCSIOp:$cond)), + (CMOVWrr (icond2cc $cond), (CPSrr $l, $r), $t, $f)>; +def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCUIOp:$cond)), + (CMOVWrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>; +def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCSIOp:$cond)), + (CMOVLrr (icond2cc $cond), (CPXrr $l, $r), $t, $f)>; +def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCUIOp:$cond)), + (CMOVLrr (icond2cc $cond), (CMPrr $l, $r), $t, $f)>; +def : Pat<(f64 (selectcc f32:$l, f32:$r, f64:$t, f64:$f, cond:$cond)), + (CMOVSrr (fcond2cc $cond), (FCPSrr $l, $r), $t, $f)>; +def : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)), + (CMOVDrr (fcond2cc $cond), (FCPrr $l, $r), $t, $f)>; + +// selectcc for f32 result +def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrr (icond2cc $cond), + (CPSrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; +def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrr (icond2cc $cond), + (CMPUWrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; +def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrr (icond2cc $cond), + (CPXrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; +def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrr (icond2cc $cond), + (CMPrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; +def : Pat<(f32 (selectcc f32:$l, f32:$r, f32:$t, f32:$f, cond:$cond)), + (EXTRACT_SUBREG + (CMOVSrr (fcond2cc $cond), + (FCPSrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; +def : Pat<(f32 (selectcc f64:$l, f64:$r, f32:$t, f32:$f, cond:$cond)), + (EXTRACT_SUBREG + (CMOVDrr (fcond2cc $cond), + (FCPrr $l, $r), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; + +// Generic SELECT pattern matches +// Use cmov.w for all cases since %pred holds i32. +// +// CMOV.w.ne %res, %tval, %tmp ; set tval if %tmp is true + +def : Pat<(i64 (select i32:$pred, i64:$t, i64:$f)), + (CMOVWrr CC_INE, $pred, $t, $f)>; + +def : Pat<(i32 (select i32:$pred, i32:$t, i32:$f)), + (EXTRACT_SUBREG + (CMOVWrr CC_INE, $pred, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)), + sub_i32)>; + +def : Pat<(f64 (select i32:$pred, f64:$t, f64:$f)), + (CMOVWrr CC_INE, $pred, $t, $f)>; + +def : Pat<(f32 (select i32:$pred, f32:$t, f32:$f)), + (EXTRACT_SUBREG + (CMOVWrr CC_INE, $pred, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_f32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_f32)), + sub_f32)>; + // Several special pattern matches to optimize code diff --git a/llvm/test/CodeGen/VE/max.ll b/llvm/test/CodeGen/VE/max.ll new file mode 100644 index 000000000000..728f6d7ab8b5 --- /dev/null +++ b/llvm/test/CodeGen/VE/max.ll @@ -0,0 +1,199 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @maxf64(double, double) { +; CHECK-LABEL: maxf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmax.d %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define double @max2f64(double, double) { +; CHECK-LABEL: max2f64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmax.d %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +; VE has no max for unordered comparison +define double @maxuf64(double, double) { +; CHECK-LABEL: maxuf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s2, %s0, %s1 +; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +; VE has no max for unordered comparison +define double @max2uf64(double, double) { +; CHECK-LABEL: max2uf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s2, %s0, %s1 +; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define float @maxf32(float, float) { +; CHECK-LABEL: maxf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmax.s %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @max2f32(float, float) { +; CHECK-LABEL: max2f32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmax.s %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @maxuf32(float, float) { +; CHECK-LABEL: maxuf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1 +; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0 +; CHECK-NEXT: fcmp.s %s2, %s0, %s1 +; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @max2uf32(float, float) { +; CHECK-LABEL: max2uf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1 +; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0 +; CHECK-NEXT: fcmp.s %s2, %s0, %s1 +; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define i64 @maxi64(i64, i64) { +; CHECK-LABEL: maxi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: maxs.l %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @max2i64(i64, i64) { +; CHECK-LABEL: max2i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: maxs.l %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @maxu64(i64, i64) { +; CHECK-LABEL: maxu64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s2, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @max2u64(i64, i64) { +; CHECK-LABEL: max2u64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s2, %s0, %s1 +; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i32 @maxi32(i32, i32) { +; CHECK-LABEL: maxi32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: maxs.w.zx %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @max2i32(i32, i32) { +; CHECK-LABEL: max2i32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: maxs.w.zx %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @maxu32(i32, i32) { +; CHECK-LABEL: maxu32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: cmpu.w %s2, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @max2u32(i32, i32) { +; CHECK-LABEL: max2u32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: cmpu.w %s2, %s0, %s1 +; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) { +; CHECK-LABEL: maxi1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, %s0, %s1 +; CHECK-NEXT: or %s0, %s1, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = xor i1 %1, true + %4 = and i1 %3, %0 + %5 = select i1 %4, i1 %0, i1 %1 + ret i1 %5 +} diff --git a/llvm/test/CodeGen/VE/min.ll b/llvm/test/CodeGen/VE/min.ll new file mode 100644 index 000000000000..7f0dee2029ab --- /dev/null +++ b/llvm/test/CodeGen/VE/min.ll @@ -0,0 +1,199 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @minf64(double, double) { +; CHECK-LABEL: minf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmin.d %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define double @min2f64(double, double) { +; CHECK-LABEL: min2f64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmin.d %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define double @minuf64(double, double) { +; CHECK-LABEL: minuf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s2, %s0, %s1 +; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define double @min2uf64(double, double) { +; CHECK-LABEL: min2uf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s2, %s0, %s1 +; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule double %0, %1 + %4 = select i1 %3, double %0, double %1 + ret double %4 +} + +define float @minf32(float, float) { +; CHECK-LABEL: minf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmin.s %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @min2f32(float, float) { +; CHECK-LABEL: min2f32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fmin.s %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @minuf32(float, float) { +; CHECK-LABEL: minuf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1 +; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0 +; CHECK-NEXT: fcmp.s %s2, %s0, %s1 +; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define float @min2uf32(float, float) { +; CHECK-LABEL: min2uf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1 +; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0 +; CHECK-NEXT: fcmp.s %s2, %s0, %s1 +; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule float %0, %1 + %4 = select i1 %3, float %0, float %1 + ret float %4 +} + +define i64 @mini64(i64, i64) { +; CHECK-LABEL: mini64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: mins.l %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @min2i64(i64, i64) { +; CHECK-LABEL: min2i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: mins.l %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @minu64(i64, i64) { +; CHECK-LABEL: minu64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s2, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i64 @min2u64(i64, i64) { +; CHECK-LABEL: min2u64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s2, %s0, %s1 +; CHECK-NEXT: cmov.l.le %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i64 %0, %1 + %4 = select i1 %3, i64 %0, i64 %1 + ret i64 %4 +} + +define i32 @mini32(i32, i32) { +; CHECK-LABEL: mini32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: mins.w.zx %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @min2i32(i32, i32) { +; CHECK-LABEL: min2i32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: mins.w.zx %s0, %s0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @minu32(i32, i32) { +; CHECK-LABEL: minu32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: cmpu.w %s2, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define i32 @min2u32(i32, i32) { +; CHECK-LABEL: min2u32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: cmpu.w %s2, %s0, %s1 +; CHECK-NEXT: cmov.w.le %s1, %s0, %s2 +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i32 %0, %1 + %4 = select i1 %3, i32 %0, i32 %1 + ret i32 %4 +} + +define zeroext i1 @mini1(i1 zeroext, i1 zeroext) { +; CHECK-LABEL: mini1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: and %s2, %s1, %s0 +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = xor i1 %0, true + %4 = and i1 %3, %1 + %5 = select i1 %4, i1 %0, i1 %1 + ret i1 %5 +} diff --git a/llvm/test/CodeGen/VE/select.ll b/llvm/test/CodeGen/VE/select.ll new file mode 100644 index 000000000000..6efe073381d5 --- /dev/null +++ b/llvm/test/CodeGen/VE/select.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @selectf64(i1 zeroext, double, double) { +; CHECK-LABEL: selectf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %4 = select i1 %0, double %1, double %2 + ret double %4 +} + +define float @selectf32(i1 zeroext, float, float) { +; CHECK-LABEL: selectf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1 +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %4 = select i1 %0, float %1, float %2 + ret float %4 +} + +define i64 @selecti64(i1 zeroext, i64, i64) { +; CHECK-LABEL: selecti64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %4 = select i1 %0, i64 %1, i64 %2 + ret i64 %4 +} + +define i32 @selecti32(i1 zeroext, i32, i32) { +; CHECK-LABEL: selecti32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %4 = select i1 %0, i32 %1, i32 %2 + ret i32 %4 +} + +define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) { +; CHECK-LABEL: selecti1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1 +; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0 +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %4 = select i1 %0, i1 %1, i1 %2 + ret i1 %4 +} diff --git a/llvm/test/CodeGen/VE/selectccf32.ll b/llvm/test/CodeGen/VE/selectccf32.ll new file mode 100644 index 000000000000..748a3e927557 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf32.ll @@ -0,0 +1,217 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define float @selectccaf(float, float, float, float) { +; CHECK-LABEL: selectccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp false float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccat(float, float, float, float) { +; CHECK-LABEL: selectccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp true float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccoeq(float, float, float, float) { +; CHECK-LABEL: selectccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oeq float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccone(float, float, float, float) { +; CHECK-LABEL: selectccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp one float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccogt(float, float, float, float) { +; CHECK-LABEL: selectccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccoge(float, float, float, float) { +; CHECK-LABEL: selectccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oge float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccolt(float, float, float, float) { +; CHECK-LABEL: selectccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp olt float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccole(float, float, float, float) { +; CHECK-LABEL: selectccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ole float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccord(float, float, float, float) { +; CHECK-LABEL: selectccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ord float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccuno(float, float, float, float) { +; CHECK-LABEL: selectccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uno float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccueq(float, float, float, float) { +; CHECK-LABEL: selectccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ueq float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccune(float, float, float, float) { +; CHECK-LABEL: selectccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp une float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccugt(float, float, float, float) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ugt float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccuge(float, float, float, float) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uge float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccult(float, float, float, float) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ult float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccule(float, float, float, float) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ule float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} diff --git a/llvm/test/CodeGen/VE/selectccf32c.ll b/llvm/test/CodeGen/VE/selectccf32c.ll new file mode 100644 index 000000000000..78a9aaf96729 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf32c.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define float @selectccsgti8(i8, i8, float, float) { +; CHECK-LABEL: selectccsgti8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: sla.w.sx %s1, %s1, 24 +; CHECK-NEXT: sra.w.sx %s1, %s1, 24 +; CHECK-NEXT: sla.w.sx %s0, %s0, 24 +; CHECK-NEXT: sra.w.sx %s0, %s0, 24 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i8 %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccsgti16(i16, i16, float, float) { +; CHECK-LABEL: selectccsgti16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: sla.w.sx %s1, %s1, 16 +; CHECK-NEXT: sra.w.sx %s1, %s1, 16 +; CHECK-NEXT: sla.w.sx %s0, %s0, 16 +; CHECK-NEXT: sra.w.sx %s0, %s0, 16 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i16 %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccsgti32(i32, i32, float, float) { +; CHECK-LABEL: selectccsgti32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccsgti64(i64, i64, float, float) { +; CHECK-LABEL: selectccsgti64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccsgti128(i128, i128, float, float) { +; CHECK-LABEL: selectccsgti128: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf5 killed $sf5 def $sx5 +; CHECK-NEXT: # kill: def $sf4 killed $sf4 def $sx4 +; CHECK-NEXT: or %s6, 0, (0)1 +; CHECK-NEXT: cmps.l %s1, %s1, %s3 +; CHECK-NEXT: or %s3, 0, %s6 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s2 +; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: or %s0, 0, %s5 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i128 %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccogtf32(float, float, float, float) { +; CHECK-LABEL: selectccogtf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccogtf64(double, double, float, float) { +; CHECK-LABEL: selectccogtf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, %1 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + diff --git a/llvm/test/CodeGen/VE/selectccf32i.ll b/llvm/test/CodeGen/VE/selectccf32i.ll new file mode 100644 index 000000000000..3725a8c068e1 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf32i.ll @@ -0,0 +1,241 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define float @selectccaf(float, float, float, float) { +; CHECK-LABEL: selectccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp false float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccat(float, float, float, float) { +; CHECK-LABEL: selectccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp true float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccoeq(float, float, float, float) { +; CHECK-LABEL: selectccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oeq float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccone(float, float, float, float) { +; CHECK-LABEL: selectccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp one float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccogt(float, float, float, float) { +; CHECK-LABEL: selectccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccoge(float, float, float, float) { +; CHECK-LABEL: selectccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oge float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccolt(float, float, float, float) { +; CHECK-LABEL: selectccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp olt float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccole(float, float, float, float) { +; CHECK-LABEL: selectccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ole float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccord(float, float, float, float) { +; CHECK-LABEL: selectccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s0 +; CHECK-NEXT: cmov.s.num %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ord float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccuno(float, float, float, float) { +; CHECK-LABEL: selectccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s0 +; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uno float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccueq(float, float, float, float) { +; CHECK-LABEL: selectccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ueq float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccune(float, float, float, float) { +; CHECK-LABEL: selectccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp une float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccugt(float, float, float, float) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ugt float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccuge(float, float, float, float) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uge float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccult(float, float, float, float) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ult float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} + +define float @selectccule(float, float, float, float) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3 +; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ule float %0, 0.0 + %6 = select i1 %5, float %2, float %3 + ret float %6 +} diff --git a/llvm/test/CodeGen/VE/selectccf64.ll b/llvm/test/CodeGen/VE/selectccf64.ll new file mode 100644 index 000000000000..76bec52cbe69 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf64.ll @@ -0,0 +1,189 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @selectccaf(double, double, double, double) { +; CHECK-LABEL: selectccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp false double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccat(double, double, double, double) { +; CHECK-LABEL: selectccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp true double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccoeq(double, double, double, double) { +; CHECK-LABEL: selectccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oeq double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccone(double, double, double, double) { +; CHECK-LABEL: selectccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp one double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccogt(double, double, double, double) { +; CHECK-LABEL: selectccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccoge(double, double, double, double) { +; CHECK-LABEL: selectccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oge double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccolt(double, double, double, double) { +; CHECK-LABEL: selectccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp olt double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccole(double, double, double, double) { +; CHECK-LABEL: selectccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ole double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccord(double, double, double, double) { +; CHECK-LABEL: selectccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ord double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccuno(double, double, double, double) { +; CHECK-LABEL: selectccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uno double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccueq(double, double, double, double) { +; CHECK-LABEL: selectccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ueq double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccune(double, double, double, double) { +; CHECK-LABEL: selectccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp une double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccugt(double, double, double, double) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ugt double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccuge(double, double, double, double) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uge double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccult(double, double, double, double) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ult double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccule(double, double, double, double) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ule double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} diff --git a/llvm/test/CodeGen/VE/selectccf64c.ll b/llvm/test/CodeGen/VE/selectccf64c.ll new file mode 100644 index 000000000000..4481d1d6197f --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf64c.ll @@ -0,0 +1,102 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @selectccsgti8(i8, i8, double, double) { +; CHECK-LABEL: selectccsgti8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: sla.w.sx %s1, %s1, 24 +; CHECK-NEXT: sra.w.sx %s1, %s1, 24 +; CHECK-NEXT: sla.w.sx %s0, %s0, 24 +; CHECK-NEXT: sra.w.sx %s0, %s0, 24 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i8 %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccsgti16(i16, i16, double, double) { +; CHECK-LABEL: selectccsgti16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: sla.w.sx %s1, %s1, 16 +; CHECK-NEXT: sra.w.sx %s1, %s1, 16 +; CHECK-NEXT: sla.w.sx %s0, %s0, 16 +; CHECK-NEXT: sra.w.sx %s0, %s0, 16 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i16 %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccsgti32(i32, i32, double, double) { +; CHECK-LABEL: selectccsgti32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccsgti64(i64, i64, double, double) { +; CHECK-LABEL: selectccsgti64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccsgti128(i128, i128, double, double) { +; CHECK-LABEL: selectccsgti128: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s6, 0, (0)1 +; CHECK-NEXT: cmps.l %s1, %s1, %s3 +; CHECK-NEXT: or %s3, 0, %s6 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s2 +; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: or %s0, 0, %s5 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i128 %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccogtf32(float, float, double, double) { +; CHECK-LABEL: selectccogtf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccogtf64(double, double, double, double) { +; CHECK-LABEL: selectccogtf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, %1 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + diff --git a/llvm/test/CodeGen/VE/selectccf64i.ll b/llvm/test/CodeGen/VE/selectccf64i.ll new file mode 100644 index 000000000000..b39ba5d07725 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectccf64i.ll @@ -0,0 +1,201 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define double @selectccaf(double, double, double, double) { +; CHECK-LABEL: selectccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp false double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccat(double, double, double, double) { +; CHECK-LABEL: selectccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp true double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccoeq(double, double, double, double) { +; CHECK-LABEL: selectccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oeq double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccone(double, double, double, double) { +; CHECK-LABEL: selectccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp one double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccogt(double, double, double, double) { +; CHECK-LABEL: selectccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccoge(double, double, double, double) { +; CHECK-LABEL: selectccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp oge double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccolt(double, double, double, double) { +; CHECK-LABEL: selectccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp olt double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccole(double, double, double, double) { +; CHECK-LABEL: selectccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ole double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccord(double, double, double, double) { +; CHECK-LABEL: selectccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s0 +; CHECK-NEXT: cmov.d.num %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ord double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccuno(double, double, double, double) { +; CHECK-LABEL: selectccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s0 +; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uno double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccueq(double, double, double, double) { +; CHECK-LABEL: selectccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ueq double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccune(double, double, double, double) { +; CHECK-LABEL: selectccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp une double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccugt(double, double, double, double) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ugt double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccuge(double, double, double, double) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp uge double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccult(double, double, double, double) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ult double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} + +define double @selectccule(double, double, double, double) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ule double %0, 0.0 + %6 = select i1 %5, double %2, double %3 + ret double %6 +} diff --git a/llvm/test/CodeGen/VE/selectcci32.ll b/llvm/test/CodeGen/VE/selectcci32.ll new file mode 100644 index 000000000000..eea115c8b936 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci32.ll @@ -0,0 +1,197 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i32 @selectcceq(i32, i32, i32, i32) { +; CHECK-LABEL: selectcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp eq i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccne(i32, i32, i32, i32) { +; CHECK-LABEL: selectccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ne i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsge(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sge i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccslt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp slt i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsle(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sle i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccugt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccuge(i32, i32, i32, i32) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccult(i32, i32, i32, i32) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccule(i32, i32, i32, i32) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccugt2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccugt2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccuge2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccuge2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccult2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccult2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccule2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccule2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} diff --git a/llvm/test/CodeGen/VE/selectcci32c.ll b/llvm/test/CodeGen/VE/selectcci32c.ll new file mode 100644 index 000000000000..474e9e0dcd4d --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci32c.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i32 @selectccsgti8(i8, i8, i32, i32) { +; CHECK-LABEL: selectccsgti8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: sla.w.sx %s1, %s1, 24 +; CHECK-NEXT: sra.w.sx %s1, %s1, 24 +; CHECK-NEXT: sla.w.sx %s0, %s0, 24 +; CHECK-NEXT: sra.w.sx %s0, %s0, 24 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i8 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgti16(i16, i16, i32, i32) { +; CHECK-LABEL: selectccsgti16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: sla.w.sx %s1, %s1, 16 +; CHECK-NEXT: sra.w.sx %s1, %s1, 16 +; CHECK-NEXT: sla.w.sx %s0, %s0, 16 +; CHECK-NEXT: sra.w.sx %s0, %s0, 16 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i16 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgti32(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsgti32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgti64(i64, i64, i32, i32) { +; CHECK-LABEL: selectccsgti64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgti128(i128, i128, i32, i32) { +; CHECK-LABEL: selectccsgti128: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw5 killed $sw5 def $sx5 +; CHECK-NEXT: # kill: def $sw4 killed $sw4 def $sx4 +; CHECK-NEXT: or %s6, 0, (0)1 +; CHECK-NEXT: cmps.l %s1, %s1, %s3 +; CHECK-NEXT: or %s3, 0, %s6 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s2 +; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: or %s0, 0, %s5 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i128 %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccogtf32(float, float, i32, i32) { +; CHECK-LABEL: selectccogtf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccogtf64(double, double, i32, i32) { +; CHECK-LABEL: selectccogtf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, %1 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + diff --git a/llvm/test/CodeGen/VE/selectcci32i.ll b/llvm/test/CodeGen/VE/selectcci32i.ll new file mode 100644 index 000000000000..0e17f83ad178 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci32i.ll @@ -0,0 +1,211 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i32 @selectcceq(i32, i32, i32, i32) { +; CHECK-LABEL: selectcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp eq i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccne(i32, i32, i32, i32) { +; CHECK-LABEL: selectccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ne i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsgt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsge(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sge i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccslt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp slt i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccsle(i32, i32, i32, i32) { +; CHECK-LABEL: selectccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sle i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccugt(i32, i32, i32, i32) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccuge(i32, i32, i32, i32) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccult(i32, i32, i32, i32) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccule(i32, i32, i32, i32) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccugt2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccugt2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccuge2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccuge2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccult2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccult2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} + +define i32 @selectccule2(i32, i32, i32, i32) { +; CHECK-LABEL: selectccule2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3 +; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2 +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.w %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i32 %0, 12 + %6 = select i1 %5, i32 %2, i32 %3 + ret i32 %6 +} diff --git a/llvm/test/CodeGen/VE/selectcci64.ll b/llvm/test/CodeGen/VE/selectcci64.ll new file mode 100644 index 000000000000..a58554772fb5 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci64.ll @@ -0,0 +1,169 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @selectcceq(i64, i64, i64, i64) { +; CHECK-LABEL: selectcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp eq i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccne(i64, i64, i64, i64) { +; CHECK-LABEL: selectccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ne i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsge(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sge i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccslt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp slt i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsle(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sle i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccugt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccuge(i64, i64, i64, i64) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccult(i64, i64, i64, i64) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccule(i64, i64, i64, i64) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccugt2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccugt2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccuge2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccuge2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccult2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccult2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccule2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccule2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.le %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} diff --git a/llvm/test/CodeGen/VE/selectcci64c.ll b/llvm/test/CodeGen/VE/selectcci64c.ll new file mode 100644 index 000000000000..7bb7d7fee1c3 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci64c.ll @@ -0,0 +1,102 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @selectccsgti8(i8, i8, i64, i64) { +; CHECK-LABEL: selectccsgti8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: sla.w.sx %s1, %s1, 24 +; CHECK-NEXT: sra.w.sx %s1, %s1, 24 +; CHECK-NEXT: sla.w.sx %s0, %s0, 24 +; CHECK-NEXT: sra.w.sx %s0, %s0, 24 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i8 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgti16(i16, i16, i64, i64) { +; CHECK-LABEL: selectccsgti16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: sla.w.sx %s1, %s1, 16 +; CHECK-NEXT: sra.w.sx %s1, %s1, 16 +; CHECK-NEXT: sla.w.sx %s0, %s0, 16 +; CHECK-NEXT: sra.w.sx %s0, %s0, 16 +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i16 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgti32(i32, i32, i64, i64) { +; CHECK-LABEL: selectccsgti32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1 +; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i32 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgti64(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsgti64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgti128(i128, i128, i64, i64) { +; CHECK-LABEL: selectccsgti128: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s6, 0, (0)1 +; CHECK-NEXT: cmps.l %s1, %s1, %s3 +; CHECK-NEXT: or %s3, 0, %s6 +; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s2 +; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0 +; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0 +; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0 +; CHECK-NEXT: or %s0, 0, %s5 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i128 %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccogtf32(float, float, i64, i64) { +; CHECK-LABEL: selectccogtf32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s0, %s0, %s1 +; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt float %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccogtf64(double, double, i64, i64) { +; CHECK-LABEL: selectccogtf64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s0, %s0, %s1 +; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = fcmp ogt double %0, %1 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + diff --git a/llvm/test/CodeGen/VE/selectcci64i.ll b/llvm/test/CodeGen/VE/selectcci64i.ll new file mode 100644 index 000000000000..cf37d9b584b9 --- /dev/null +++ b/llvm/test/CodeGen/VE/selectcci64i.ll @@ -0,0 +1,183 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @selectcceq(i64, i64, i64, i64) { +; CHECK-LABEL: selectcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp eq i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccne(i64, i64, i64, i64) { +; CHECK-LABEL: selectccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ne i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsgt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sgt i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsge(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sge i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccslt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp slt i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccsle(i64, i64, i64, i64) { +; CHECK-LABEL: selectccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmps.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp sle i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccugt(i64, i64, i64, i64) { +; CHECK-LABEL: selectccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccuge(i64, i64, i64, i64) { +; CHECK-LABEL: selectccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccult(i64, i64, i64, i64) { +; CHECK-LABEL: selectccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccule(i64, i64, i64, i64) { +; CHECK-LABEL: selectccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccugt2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccugt2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ugt i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccuge2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccuge2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp uge i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccult2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccult2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ult i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +} + +define i64 @selectccule2(i64, i64, i64, i64) { +; CHECK-LABEL: selectccule2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.l %s0, %s0, %s1 +; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0 +; CHECK-NEXT: or %s0, 0, %s3 +; CHECK-NEXT: or %s11, 0, %s9 + %5 = icmp ule i64 %0, 12 + %6 = select i1 %5, i64 %2, i64 %3 + ret i64 %6 +}