forked from OSchip/llvm-project
parent
958feffa11
commit
83a6188f18
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@ -2794,20 +2794,19 @@ def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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}
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def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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"dsb", "\t$opt",
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[/* For disassembly only; pattern left blank */]>,
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"dsb", "\t$opt", []>,
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Requires<[IsThumb, HasDB]> {
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bits<4> opt;
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let Inst{31-4} = 0xf3bf8f4;
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let Inst{3-0} = opt;
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}
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// ISB has only full system option -- for disassembly only
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def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsThumb2, HasV7]> {
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def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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"isb", "\t$opt",
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[]>, Requires<[IsThumb2, HasV7]> {
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bits<4> opt;
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let Inst{31-4} = 0xf3bf8f6;
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let Inst{3-0} = 0b1111;
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let Inst{3-0} = opt;
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}
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class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
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@ -3591,4 +3590,4 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
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// Memory barriers
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def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
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def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
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//def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
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def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
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@ -452,6 +452,16 @@ _func:
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@ CHECK: eor.w r4, r5, r6, ror #5 @ encoding: [0x85,0xea,0x76,0x14]
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@------------------------------------------------------------------------------
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@ ISB
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@------------------------------------------------------------------------------
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isb sy
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isb
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@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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@------------------------------------------------------------------------------
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@ IT
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@------------------------------------------------------------------------------
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