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[AMDGPU][NFC] Update auto-gen test 

Most likely the "glc" was not added to the test when
the volatile loads started generating those bits.
This commit is contained in:
Piotr Sobczak 2021-04-23 16:19:04 +02:00
parent 8ebdb58aac
commit 83a3395b30
1 changed files with 3 additions and 3 deletions
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6
llvm/test/CodeGen/AMDGPU/multilevel-break.ll
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@ -196,7 +196,7 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
; GCN-NEXT: s_cbranch_execz BB1_9
; GCN-NEXT: BB1_2: ; %bb1
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GCN-NEXT: s_mov_b64 s[6:7], -1
@ -213,7 +213,7 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
; GCN-NEXT: s_cbranch_vccz BB1_5
; GCN-NEXT: ; %bb.4: ; %case1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2
; GCN-NEXT: s_mov_b64 s[8:9], 0
@ -233,7 +233,7 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
; GCN-NEXT: s_cbranch_vccz BB1_1
; GCN-NEXT: ; %bb.8: ; %case0
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], 0
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1