forked from OSchip/llvm-project
[RISCV] Scheduler description for the Rocket core
Pipeline scheduler model for the RISC-V Rocket micro-architecture using the MIScheduler interface. Support for both 32 and 64-bit Rocket cores is implemented. Differential revision: https://reviews.llvm.org/D68685
This commit is contained in:
Kai Wang
Evandro Menezes
parent
90e630a95e
commit
838a28e234
|
|
@ -92,10 +92,13 @@ include "RISCVSystemOperands.td"
|
|||
// Registers, calling conventions, instruction descriptions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "RISCVSchedule.td"
|
||||
include "RISCVRegisterInfo.td"
|
||||
include "RISCVCallingConv.td"
|
||||
include "RISCVInstrInfo.td"
|
||||
include "RISCVRegisterBanks.td"
|
||||
include "RISCVSchedRocket32.td"
|
||||
include "RISCVSchedRocket64.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// RISC-V processors supported.
|
||||
|
|
@ -106,6 +109,12 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
|
|||
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
|
||||
FeatureRVCHints]>;
|
||||
|
||||
def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
|
||||
|
||||
def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
|
||||
FeatureRVCHints]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define the RISC-V target.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -103,7 +103,8 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
|
|||
|
||||
// Pseudo instructions
|
||||
class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
|
||||
: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
|
||||
: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo>,
|
||||
Sched<[]> {
|
||||
let isPseudo = 1;
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -298,7 +298,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|||
class BranchCC_rri<bits<3> funct3, string opcodestr>
|
||||
: RVInstB<funct3, OPC_BRANCH, (outs),
|
||||
(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
|
||||
opcodestr, "$rs1, $rs2, $imm12"> {
|
||||
opcodestr, "$rs1, $rs2, $imm12">,
|
||||
Sched<[WriteJmp]> {
|
||||
let isBranch = 1;
|
||||
let isTerminator = 1;
|
||||
}
|
||||
|
|
@ -320,13 +321,15 @@ class Store_rri<bits<3> funct3, string opcodestr>
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class ALU_ri<bits<3> funct3, string opcodestr>
|
||||
: RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
|
||||
opcodestr, "$rd, $rs1, $imm12">;
|
||||
opcodestr, "$rd, $rs1, $imm12">,
|
||||
Sched<[WriteIALU, ReadIALU]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr>
|
||||
: RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
|
||||
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
|
||||
"$rd, $rs1, $shamt">;
|
||||
"$rd, $rs1, $shamt">,
|
||||
Sched<[WriteShift, ReadShift]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||||
|
|
@ -336,19 +339,20 @@ class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
|||
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
|
||||
class CSR_ir<bits<3> funct3, string opcodestr>
|
||||
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
|
||||
opcodestr, "$rd, $imm12, $rs1">;
|
||||
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
|
||||
|
||||
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
|
||||
class CSR_ii<bits<3> funct3, string opcodestr>
|
||||
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
|
||||
(ins csr_sysreg:$imm12, uimm5:$rs1),
|
||||
opcodestr, "$rd, $imm12, $rs1">;
|
||||
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr>
|
||||
: RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
|
||||
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
|
||||
"$rd, $rs1, $shamt">;
|
||||
"$rd, $rs1, $shamt">,
|
||||
Sched<[WriteShift32, ReadShift32]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||||
|
|
@ -367,19 +371,20 @@ class Priv<string opcodestr, bits<7> funct7>
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
||||
def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
|
||||
"lui", "$rd, $imm20">;
|
||||
"lui", "$rd, $imm20">, Sched<[WriteIALU]>;
|
||||
|
||||
def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
|
||||
"auipc", "$rd, $imm20">;
|
||||
"auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
|
||||
|
||||
let isCall = 1 in
|
||||
def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
|
||||
"jal", "$rd, $imm20">;
|
||||
"jal", "$rd, $imm20">, Sched<[WriteJal]>;
|
||||
|
||||
let isCall = 1 in
|
||||
def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
|
||||
(ins GPR:$rs1, simm12:$imm12),
|
||||
"jalr", "$rd, ${imm12}(${rs1})">;
|
||||
"jalr", "$rd, ${imm12}(${rs1})">,
|
||||
Sched<[WriteJalr, ReadJalr]>;
|
||||
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
|
||||
|
||||
def BEQ : BranchCC_rri<0b000, "beq">;
|
||||
|
|
@ -389,15 +394,15 @@ def BGE : BranchCC_rri<0b101, "bge">;
|
|||
def BLTU : BranchCC_rri<0b110, "bltu">;
|
||||
def BGEU : BranchCC_rri<0b111, "bgeu">;
|
||||
|
||||
def LB : Load_ri<0b000, "lb">;
|
||||
def LH : Load_ri<0b001, "lh">;
|
||||
def LW : Load_ri<0b010, "lw">;
|
||||
def LBU : Load_ri<0b100, "lbu">;
|
||||
def LHU : Load_ri<0b101, "lhu">;
|
||||
def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
|
||||
def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
|
||||
def LW : Load_ri<0b010, "lw">, Sched<[WriteLDW, ReadMemBase]>;
|
||||
def LBU : Load_ri<0b100, "lbu">, Sched<[WriteLDB, ReadMemBase]>;
|
||||
def LHU : Load_ri<0b101, "lhu">, Sched<[WriteLDH, ReadMemBase]>;
|
||||
|
||||
def SB : Store_rri<0b000, "sb">;
|
||||
def SH : Store_rri<0b001, "sh">;
|
||||
def SW : Store_rri<0b010, "sw">;
|
||||
def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
|
||||
def SH : Store_rri<0b001, "sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
|
||||
def SW : Store_rri<0b010, "sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
|
||||
|
||||
// ADDI isn't always rematerializable, but isReMaterializable will be used as
|
||||
// a hint which is verified in isReallyTriviallyReMaterializable.
|
||||
|
|
@ -418,21 +423,21 @@ def SLLI : Shift_ri<0, 0b001, "slli">;
|
|||
def SRLI : Shift_ri<0, 0b101, "srli">;
|
||||
def SRAI : Shift_ri<1, 0b101, "srai">;
|
||||
|
||||
def ADD : ALU_rr<0b0000000, 0b000, "add">;
|
||||
def SUB : ALU_rr<0b0100000, 0b000, "sub">;
|
||||
def SLL : ALU_rr<0b0000000, 0b001, "sll">;
|
||||
def SLT : ALU_rr<0b0000000, 0b010, "slt">;
|
||||
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
|
||||
def XOR : ALU_rr<0b0000000, 0b100, "xor">;
|
||||
def SRL : ALU_rr<0b0000000, 0b101, "srl">;
|
||||
def SRA : ALU_rr<0b0100000, 0b101, "sra">;
|
||||
def OR : ALU_rr<0b0000000, 0b110, "or">;
|
||||
def AND : ALU_rr<0b0000000, 0b111, "and">;
|
||||
def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
|
||||
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
|
||||
def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
|
||||
(ins fencearg:$pred, fencearg:$succ),
|
||||
"fence", "$pred, $succ"> {
|
||||
"fence", "$pred, $succ">, Sched<[]> {
|
||||
bits<4> pred;
|
||||
bits<4> succ;
|
||||
|
||||
|
|
@ -441,25 +446,26 @@ def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
|
|||
let imm12 = {0b0000,pred,succ};
|
||||
}
|
||||
|
||||
def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", ""> {
|
||||
def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
|
||||
let rs1 = 0;
|
||||
let rd = 0;
|
||||
let imm12 = {0b1000,0b0011,0b0011};
|
||||
}
|
||||
|
||||
def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", ""> {
|
||||
def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
|
||||
let rs1 = 0;
|
||||
let rd = 0;
|
||||
let imm12 = 0;
|
||||
}
|
||||
|
||||
def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", ""> {
|
||||
def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> {
|
||||
let rs1 = 0;
|
||||
let rd = 0;
|
||||
let imm12 = 0;
|
||||
}
|
||||
|
||||
def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
|
||||
def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", "">,
|
||||
Sched<[]> {
|
||||
let rs1 = 0;
|
||||
let rd = 0;
|
||||
let imm12 = 1;
|
||||
|
|
@ -468,7 +474,8 @@ def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
|
|||
// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
|
||||
// instruction (i.e., it should always trap, if your implementation has invalid
|
||||
// instruction traps).
|
||||
def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> {
|
||||
def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
|
||||
Sched<[]> {
|
||||
let rs1 = 0;
|
||||
let rd = 0;
|
||||
let imm12 = 0b110000000000;
|
||||
|
|
@ -486,24 +493,30 @@ def CSRRCI : CSR_ii<0b111, "csrrci">;
|
|||
/// RV64I instructions
|
||||
|
||||
let Predicates = [IsRV64] in {
|
||||
def LWU : Load_ri<0b110, "lwu">;
|
||||
def LD : Load_ri<0b011, "ld">;
|
||||
def SD : Store_rri<0b011, "sd">;
|
||||
def LWU : Load_ri<0b110, "lwu">, Sched<[WriteLDWU, ReadMemBase]>;
|
||||
def LD : Load_ri<0b011, "ld">, Sched<[WriteLDD, ReadMemBase]>;
|
||||
def SD : Store_rri<0b011, "sd">, Sched<[WriteSTD, ReadStoreData, ReadMemBase]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
|
||||
(ins GPR:$rs1, simm12:$imm12),
|
||||
"addiw", "$rd, $rs1, $imm12">;
|
||||
"addiw", "$rd, $rs1, $imm12">,
|
||||
Sched<[WriteIALU32, ReadIALU32]>;
|
||||
|
||||
def SLLIW : ShiftW_ri<0, 0b001, "slliw">;
|
||||
def SRLIW : ShiftW_ri<0, 0b101, "srliw">;
|
||||
def SRAIW : ShiftW_ri<1, 0b101, "sraiw">;
|
||||
|
||||
def ADDW : ALUW_rr<0b0000000, 0b000, "addw">;
|
||||
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">;
|
||||
def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">;
|
||||
def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">;
|
||||
def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">;
|
||||
def ADDW : ALUW_rr<0b0000000, 0b000, "addw">,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
} // Predicates = [IsRV64]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -511,26 +524,26 @@ def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">;
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
|
||||
def URET : Priv<"uret", 0b0000000> {
|
||||
def URET : Priv<"uret", 0b0000000>, Sched<[]> {
|
||||
let rd = 0;
|
||||
let rs1 = 0;
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
|
||||
def SRET : Priv<"sret", 0b0001000> {
|
||||
def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
|
||||
let rd = 0;
|
||||
let rs1 = 0;
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
|
||||
def MRET : Priv<"mret", 0b0011000> {
|
||||
def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
|
||||
let rd = 0;
|
||||
let rs1 = 0;
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
} // isBarrier = 1, isReturn = 1, isTerminator = 1
|
||||
|
||||
def WFI : Priv<"wfi", 0b0001000> {
|
||||
def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
|
||||
let rd = 0;
|
||||
let rs1 = 0;
|
||||
let rs2 = 0b00101;
|
||||
|
|
@ -539,7 +552,7 @@ def WFI : Priv<"wfi", 0b0001000> {
|
|||
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
|
||||
def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
|
||||
(ins GPR:$rs1, GPR:$rs2),
|
||||
"sfence.vma", "$rs1, $rs2"> {
|
||||
"sfence.vma", "$rs1, $rs2">, Sched<[]> {
|
||||
let rd = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -77,31 +77,51 @@ multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Predicates = [HasStdExtA] in {
|
||||
defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
|
||||
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
|
||||
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
|
||||
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
|
||||
defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
|
||||
defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
|
||||
defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
|
||||
defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
|
||||
defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
|
||||
defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
|
||||
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
|
||||
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
|
||||
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
|
||||
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
|
||||
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
|
||||
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
|
||||
} // Predicates = [HasStdExtA]
|
||||
|
||||
let Predicates = [HasStdExtA, IsRV64] in {
|
||||
defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
|
||||
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
|
||||
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
|
||||
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
|
||||
defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
|
||||
defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
|
||||
defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
|
||||
defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
|
||||
defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
|
||||
defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
|
||||
defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
|
||||
defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
|
||||
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">,
|
||||
Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
|
||||
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
|
||||
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
|
||||
} // Predicates = [HasStdExtA, IsRV64]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -282,7 +282,8 @@ let Predicates = [HasStdExtC] in {
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [X2] in
|
||||
def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
|
||||
(ins SP:$rs1, uimm10_lsb00nonzero:$imm),
|
||||
"c.addi4spn", "$rd, $rs1, $imm"> {
|
||||
"c.addi4spn", "$rd, $rs1, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
bits<5> rs1;
|
||||
let Inst{12-11} = imm{5-4};
|
||||
let Inst{10-7} = imm{9-6};
|
||||
|
|
@ -291,13 +292,15 @@ def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
|
|||
}
|
||||
|
||||
let Predicates = [HasStdExtC, HasStdExtD] in
|
||||
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000> {
|
||||
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
|
||||
Sched<[WriteFLD64, ReadMemBase]> {
|
||||
bits<8> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6-5} = imm{7-6};
|
||||
}
|
||||
|
||||
def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00> {
|
||||
def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
|
||||
Sched<[WriteLDW, ReadMemBase]> {
|
||||
bits<7> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6} = imm{2};
|
||||
|
|
@ -306,7 +309,8 @@ def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00> {
|
|||
|
||||
let DecoderNamespace = "RISCV32Only_",
|
||||
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
||||
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00> {
|
||||
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
|
||||
Sched<[WriteFLD32, ReadMemBase]> {
|
||||
bits<7> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6} = imm{2};
|
||||
|
|
@ -314,20 +318,23 @@ def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00> {
|
|||
}
|
||||
|
||||
let Predicates = [HasStdExtC, IsRV64] in
|
||||
def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000> {
|
||||
def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
|
||||
Sched<[WriteLDD, ReadMemBase]> {
|
||||
bits<8> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6-5} = imm{7-6};
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtC, HasStdExtD] in
|
||||
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000> {
|
||||
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
|
||||
Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
|
||||
bits<8> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6-5} = imm{7-6};
|
||||
}
|
||||
|
||||
def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00> {
|
||||
def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
|
||||
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
|
||||
bits<7> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6} = imm{2};
|
||||
|
|
@ -336,7 +343,8 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00> {
|
|||
|
||||
let DecoderNamespace = "RISCV32Only_",
|
||||
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
||||
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00> {
|
||||
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
|
||||
Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
|
||||
bits<7> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6} = imm{2};
|
||||
|
|
@ -344,14 +352,16 @@ def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00> {
|
|||
}
|
||||
|
||||
let Predicates = [HasStdExtC, IsRV64] in
|
||||
def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000> {
|
||||
def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
|
||||
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
|
||||
bits<8> imm;
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{6-5} = imm{7-6};
|
||||
}
|
||||
|
||||
let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">
|
||||
def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
|
||||
Sched<[WriteNop]>
|
||||
{
|
||||
let Inst{6-2} = 0;
|
||||
}
|
||||
|
|
@ -359,7 +369,8 @@ def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
|
||||
(ins GPRNoX0:$rd, simm6nonzero:$imm),
|
||||
"c.addi", "$rd, $imm"> {
|
||||
"c.addi", "$rd, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
|
@ -367,7 +378,8 @@ def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
|
||||
(ins GPRX0:$rd, immzero:$imm),
|
||||
"c.addi", "$rd, $imm"> {
|
||||
"c.addi", "$rd, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = 0;
|
||||
let isAsmParserOnly = 1;
|
||||
|
|
@ -377,27 +389,30 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
|
|||
DecoderNamespace = "RISCV32Only_", Defs = [X1],
|
||||
Predicates = [HasStdExtC, IsRV32] in
|
||||
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
|
||||
"c.jal", "$offset">;
|
||||
"c.jal", "$offset">, Sched<[WriteJal]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
|
||||
Predicates = [HasStdExtC, IsRV64] in
|
||||
def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
|
||||
(ins GPRNoX0:$rd, simm6:$imm),
|
||||
"c.addiw", "$rd, $imm"> {
|
||||
"c.addiw", "$rd, $imm">,
|
||||
Sched<[WriteIALU32, ReadIALU32]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
|
||||
"c.li", "$rd, $imm"> {
|
||||
"c.li", "$rd, $imm">,
|
||||
Sched<[WriteIALU]> {
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
|
||||
(ins SP:$rd, simm10_lsb0000nonzero:$imm),
|
||||
"c.addi16sp", "$rd, $imm"> {
|
||||
"c.addi16sp", "$rd, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{12} = imm{9};
|
||||
let Inst{11-7} = 2;
|
||||
|
|
@ -410,78 +425,93 @@ def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
|
||||
(ins c_lui_imm:$imm),
|
||||
"c.lui", "$rd, $imm"> {
|
||||
"c.lui", "$rd, $imm">,
|
||||
Sched<[WriteIALU]> {
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
||||
def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>;
|
||||
def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>;
|
||||
def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>,
|
||||
Sched<[WriteShift, ReadShift]>;
|
||||
def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
|
||||
Sched<[WriteShift, ReadShift]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
|
||||
"c.andi", "$rs1, $imm"> {
|
||||
"c.andi", "$rs1, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rs1 = $rs1_wb";
|
||||
let Inst{12} = imm{5};
|
||||
let Inst{11-10} = 0b10;
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
||||
def C_SUB : CS_ALU<0b100011, 0b00, "c.sub", GPRC>;
|
||||
def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>;
|
||||
def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>;
|
||||
def C_AND : CS_ALU<0b100011, 0b11, "c.and", GPRC>;
|
||||
def C_SUB : CS_ALU<0b100011, 0b00, "c.sub", GPRC>,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def C_XOR : CS_ALU<0b100011, 0b01, "c.xor", GPRC>,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
def C_AND : CS_ALU<0b100011, 0b11, "c.and", GPRC>,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
|
||||
|
||||
let Predicates = [HasStdExtC, IsRV64] in {
|
||||
def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>;
|
||||
def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>;
|
||||
def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>,
|
||||
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
|
||||
}
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
|
||||
"c.j", "$offset"> {
|
||||
"c.j", "$offset">, Sched<[WriteJmp]> {
|
||||
let isBranch = 1;
|
||||
let isTerminator=1;
|
||||
let isBarrier=1;
|
||||
}
|
||||
|
||||
def C_BEQZ : Bcz<0b110, "c.beqz", seteq, GPRC>;
|
||||
def C_BNEZ : Bcz<0b111, "c.bnez", setne, GPRC>;
|
||||
def C_BEQZ : Bcz<0b110, "c.beqz", seteq, GPRC>, Sched<[WriteJmp]>;
|
||||
def C_BNEZ : Bcz<0b111, "c.bnez", setne, GPRC>, Sched<[WriteJmp]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
|
||||
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
|
||||
"c.slli" ,"$rd, $imm"> {
|
||||
"c.slli" ,"$rd, $imm">,
|
||||
Sched<[WriteShift, ReadShift]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = imm{4-0};
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtC, HasStdExtD] in
|
||||
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000> {
|
||||
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
|
||||
Sched<[WriteFLD64, ReadMemBase]> {
|
||||
let Inst{6-5} = imm{4-3};
|
||||
let Inst{4-2} = imm{8-6};
|
||||
}
|
||||
|
||||
def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00> {
|
||||
def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
|
||||
Sched<[WriteLDW, ReadMemBase]> {
|
||||
let Inst{6-4} = imm{4-2};
|
||||
let Inst{3-2} = imm{7-6};
|
||||
}
|
||||
|
||||
let DecoderNamespace = "RISCV32Only_",
|
||||
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
||||
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00> {
|
||||
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
|
||||
Sched<[WriteFLD32, ReadMemBase]> {
|
||||
let Inst{6-4} = imm{4-2};
|
||||
let Inst{3-2} = imm{7-6};
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtC, IsRV64] in
|
||||
def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000> {
|
||||
def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
|
||||
Sched<[WriteLDD, ReadMemBase]> {
|
||||
let Inst{6-5} = imm{4-3};
|
||||
let Inst{4-2} = imm{8-6};
|
||||
}
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
|
||||
"c.jr", "$rs1"> {
|
||||
"c.jr", "$rs1">, Sched<[WriteJmpReg]> {
|
||||
let isBranch = 1;
|
||||
let isBarrier = 1;
|
||||
let isTerminator = 1;
|
||||
|
|
@ -491,43 +521,49 @@ def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
|
|||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
|
||||
"c.mv", "$rs1, $rs2">;
|
||||
"c.mv", "$rs1, $rs2">,
|
||||
Sched<[WriteIALU, ReadIALU]>;
|
||||
|
||||
let rs1 = 0, rs2 = 0, hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
|
||||
def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">;
|
||||
def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
|
||||
isCall=1, Defs=[X1], rs2 = 0 in
|
||||
def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
|
||||
"c.jalr", "$rs1">;
|
||||
"c.jalr", "$rs1">, Sched<[WriteJalr, ReadJalr]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
|
||||
(ins GPRNoX0:$rs1, GPRNoX0:$rs2),
|
||||
"c.add", "$rs1, $rs2"> {
|
||||
"c.add", "$rs1, $rs2">,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
|
||||
let Constraints = "$rs1 = $rs1_wb";
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtC, HasStdExtD] in
|
||||
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000> {
|
||||
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
|
||||
Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{9-7} = imm{8-6};
|
||||
}
|
||||
|
||||
def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00> {
|
||||
def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
|
||||
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
|
||||
let Inst{12-9} = imm{5-2};
|
||||
let Inst{8-7} = imm{7-6};
|
||||
}
|
||||
|
||||
let DecoderNamespace = "RISCV32Only_",
|
||||
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
||||
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00> {
|
||||
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
|
||||
Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
|
||||
let Inst{12-9} = imm{5-2};
|
||||
let Inst{8-7} = imm{7-6};
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtC, IsRV64] in
|
||||
def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000> {
|
||||
def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
|
||||
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
|
||||
let Inst{12-10} = imm{5-3};
|
||||
let Inst{9-7} = imm{8-6};
|
||||
}
|
||||
|
|
@ -535,7 +571,8 @@ def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000> {
|
|||
// The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU
|
||||
// binutils as 16-bit instruction known to be unimplemented (i.e., trapping).
|
||||
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
|
||||
def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
|
||||
def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
|
||||
Sched<[]> {
|
||||
let Inst{15-0} = 0;
|
||||
}
|
||||
|
||||
|
|
@ -551,7 +588,7 @@ let Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
|
|||
|
||||
let rd = 0 in
|
||||
def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
|
||||
"c.nop", "$imm"> {
|
||||
"c.nop", "$imm">, Sched<[WriteNop]> {
|
||||
let Inst{6-2} = imm{4-0};
|
||||
let DecoderMethod = "decodeRVCInstrSImm";
|
||||
}
|
||||
|
|
@ -559,7 +596,8 @@ def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
|
|||
// Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
|
||||
def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
|
||||
(ins GPRX0:$rd, simm6nonzero:$imm),
|
||||
"c.addi", "$rd, $imm"> {
|
||||
"c.addi", "$rd, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = imm{4-0};
|
||||
let isAsmParserOnly = 1;
|
||||
|
|
@ -567,14 +605,16 @@ def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
|
|||
|
||||
def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
|
||||
(ins GPRNoX0:$rd, immzero:$imm),
|
||||
"c.addi", "$rd, $imm"> {
|
||||
"c.addi", "$rd, $imm">,
|
||||
Sched<[WriteIALU, ReadIALU]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = 0;
|
||||
let isAsmParserOnly = 1;
|
||||
}
|
||||
|
||||
def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
|
||||
"c.li", "$rd, $imm"> {
|
||||
"c.li", "$rd, $imm">,
|
||||
Sched<[WriteIALU]> {
|
||||
let Inst{6-2} = imm{4-0};
|
||||
let Inst{11-7} = 0;
|
||||
let DecoderMethod = "decodeRVCInstrRdSImm";
|
||||
|
|
@ -582,14 +622,15 @@ def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
|
|||
|
||||
def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
|
||||
(ins c_lui_imm:$imm),
|
||||
"c.lui", "$rd, $imm"> {
|
||||
"c.lui", "$rd, $imm">,
|
||||
Sched<[WriteIALU]> {
|
||||
let Inst{6-2} = imm{4-0};
|
||||
let Inst{11-7} = 0;
|
||||
let DecoderMethod = "decodeRVCInstrRdSImm";
|
||||
}
|
||||
|
||||
def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
|
||||
"c.mv", "$rs1, $rs2">
|
||||
"c.mv", "$rs1, $rs2">, Sched<[WriteIALU, ReadIALU]>
|
||||
{
|
||||
let Inst{11-7} = 0;
|
||||
let DecoderMethod = "decodeRVCInstrRdRs2";
|
||||
|
|
@ -597,7 +638,8 @@ def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
|
|||
|
||||
def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
|
||||
(ins GPRX0:$rs1, GPRNoX0:$rs2),
|
||||
"c.add", "$rs1, $rs2"> {
|
||||
"c.add", "$rs1, $rs2">,
|
||||
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
|
||||
let Constraints = "$rs1 = $rs1_wb";
|
||||
let Inst{11-7} = 0;
|
||||
let DecoderMethod = "decodeRVCInstrRdRs1Rs2";
|
||||
|
|
@ -605,7 +647,8 @@ def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
|
|||
|
||||
def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
|
||||
(ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
|
||||
"c.slli" ,"$rd, $imm"> {
|
||||
"c.slli" ,"$rd, $imm">,
|
||||
Sched<[WriteShift, ReadShift]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = imm{4-0};
|
||||
let Inst{11-7} = 0;
|
||||
|
|
@ -613,7 +656,8 @@ def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
|
|||
}
|
||||
|
||||
def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
|
||||
"c.slli64" ,"$rd"> {
|
||||
"c.slli64" ,"$rd">,
|
||||
Sched<[WriteShift, ReadShift]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = 0;
|
||||
let Inst{12} = 0;
|
||||
|
|
@ -621,7 +665,8 @@ def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
|
|||
|
||||
def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
|
||||
(ins GPRC:$rd),
|
||||
"c.srli64", "$rd"> {
|
||||
"c.srli64", "$rd">,
|
||||
Sched<[WriteShift, ReadShift]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = 0;
|
||||
let Inst{11-10} = 0;
|
||||
|
|
@ -630,7 +675,8 @@ def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
|
|||
|
||||
def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
|
||||
(ins GPRC:$rd),
|
||||
"c.srai64", "$rd"> {
|
||||
"c.srai64", "$rd">,
|
||||
Sched<[WriteShift, ReadShift]> {
|
||||
let Constraints = "$rd = $rd_wb";
|
||||
let Inst{6-2} = 0;
|
||||
let Inst{11-10} = 1;
|
||||
|
|
|
|||
|
|
@ -42,13 +42,15 @@ class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr>
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||||
: RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
|
||||
(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
|
||||
(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
|
||||
Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
|
||||
: RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
|
||||
(ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
|
||||
"$rd, $rs1, $rs2, $funct3">;
|
||||
"$rd, $rs1, $rs2, $funct3">,
|
||||
Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
|
||||
|
||||
class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
|
||||
: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
|
||||
|
|
@ -57,7 +59,8 @@ class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPCmpD_rr<bits<3> funct3, string opcodestr>
|
||||
: RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
|
||||
(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
|
||||
(ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
|
||||
Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
|
|
@ -68,7 +71,8 @@ let Predicates = [HasStdExtD] in {
|
|||
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
|
||||
def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
|
||||
(ins GPR:$rs1, simm12:$imm12),
|
||||
"fld", "$rd, ${imm12}(${rs1})">;
|
||||
"fld", "$rd, ${imm12}(${rs1})">,
|
||||
Sched<[WriteFLD64, ReadMemBase]>;
|
||||
|
||||
// Operands for stores are in the order srcreg, base, offset rather than
|
||||
// reflecting the order these fields are specified in the instruction
|
||||
|
|
@ -76,15 +80,20 @@ def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
|
||||
def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
|
||||
(ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
|
||||
"fsd", "$rs2, ${imm12}(${rs1})">;
|
||||
"fsd", "$rs2, ${imm12}(${rs1})">,
|
||||
Sched<[WriteFST64, ReadStoreData, ReadMemBase]>;
|
||||
|
||||
def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">;
|
||||
def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
|
||||
Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
|
||||
def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
|
||||
def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">;
|
||||
def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
|
||||
Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
|
||||
def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
|
||||
def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">;
|
||||
def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
|
||||
Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
|
||||
def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
|
||||
def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">;
|
||||
def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
|
||||
Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
|
||||
def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
|
||||
|
||||
def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">;
|
||||
|
|
@ -96,7 +105,8 @@ def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
|
|||
def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">;
|
||||
def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
|
||||
|
||||
def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d"> {
|
||||
def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
|
||||
Sched<[WriteFSqrt32, ReadFSqrt32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
|
||||
|
|
@ -107,12 +117,14 @@ def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">;
|
|||
def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">;
|
||||
def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">;
|
||||
|
||||
def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d"> {
|
||||
def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">,
|
||||
Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> {
|
||||
let rs2 = 0b00001;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
|
||||
|
||||
def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> {
|
||||
def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
|
||||
Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
|
|
@ -120,55 +132,66 @@ def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
|
|||
def FLT_D : FPCmpD_rr<0b001, "flt.d">;
|
||||
def FLE_D : FPCmpD_rr<0b000, "fle.d">;
|
||||
|
||||
def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d"> {
|
||||
def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
|
||||
Sched<[WriteFClass64, ReadFClass64]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> {
|
||||
def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
|
||||
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
|
||||
|
||||
def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> {
|
||||
def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
|
||||
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> {
|
||||
let rs2 = 0b00001;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
|
||||
|
||||
def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> {
|
||||
def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
|
||||
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> {
|
||||
def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
|
||||
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> {
|
||||
let rs2 = 0b00001;
|
||||
}
|
||||
} // Predicates = [HasStdExtD]
|
||||
|
||||
let Predicates = [HasStdExtD, IsRV64] in {
|
||||
def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d"> {
|
||||
def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">,
|
||||
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>;
|
||||
|
||||
def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d"> {
|
||||
def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">,
|
||||
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> {
|
||||
let rs2 = 0b00011;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>;
|
||||
|
||||
def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d"> {
|
||||
def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
|
||||
Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l"> {
|
||||
def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">,
|
||||
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>;
|
||||
|
||||
def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu"> {
|
||||
def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">,
|
||||
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> {
|
||||
let rs2 = 0b00011;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>;
|
||||
|
||||
def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> {
|
||||
def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
|
||||
Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
} // Predicates = [HasStdExtD, IsRV64]
|
||||
|
|
|
|||
|
|
@ -60,7 +60,8 @@ class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr>
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||||
: RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
|
||||
(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
|
||||
(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">,
|
||||
Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPALUS_rr_frm<bits<7> funct7, string opcodestr>
|
||||
|
|
@ -93,7 +94,8 @@ class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
||||
class FPCmpS_rr<bits<3> funct3, string opcodestr>
|
||||
: RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
|
||||
(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
|
||||
(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">,
|
||||
Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
|
|
@ -103,7 +105,8 @@ let Predicates = [HasStdExtF] in {
|
|||
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
|
||||
def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
|
||||
(ins GPR:$rs1, simm12:$imm12),
|
||||
"flw", "$rd, ${imm12}(${rs1})">;
|
||||
"flw", "$rd, ${imm12}(${rs1})">,
|
||||
Sched<[WriteFLD32, ReadMemBase]>;
|
||||
|
||||
// Operands for stores are in the order srcreg, base, offset rather than
|
||||
// reflecting the order these fields are specified in the instruction
|
||||
|
|
@ -111,27 +114,37 @@ def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
|
||||
def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
|
||||
(ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
|
||||
"fsw", "$rs2, ${imm12}(${rs1})">;
|
||||
"fsw", "$rs2, ${imm12}(${rs1})">,
|
||||
Sched<[WriteFST32, ReadStoreData, ReadMemBase]>;
|
||||
|
||||
def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">;
|
||||
def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">,
|
||||
Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
|
||||
def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">;
|
||||
def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">;
|
||||
def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">,
|
||||
Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
|
||||
def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">;
|
||||
def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">;
|
||||
def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">,
|
||||
Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
|
||||
def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">;
|
||||
def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">;
|
||||
def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">,
|
||||
Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
|
||||
def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">;
|
||||
|
||||
def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">;
|
||||
def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
|
||||
Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
|
||||
def : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
|
||||
def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">;
|
||||
def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
|
||||
Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
|
||||
def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
|
||||
def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">;
|
||||
def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
|
||||
Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
|
||||
def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
|
||||
def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">;
|
||||
def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
|
||||
Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
|
||||
def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
|
||||
|
||||
def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s"> {
|
||||
def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
|
||||
Sched<[WriteFSqrt32, ReadFSqrt32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
|
||||
|
|
@ -142,17 +155,20 @@ def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">;
|
|||
def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">;
|
||||
def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">;
|
||||
|
||||
def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s"> {
|
||||
def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
|
||||
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
|
||||
|
||||
def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s"> {
|
||||
def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
|
||||
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
|
||||
let rs2 = 0b00001;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
|
||||
|
||||
def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w"> {
|
||||
def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
|
||||
Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
|
|
@ -160,42 +176,50 @@ def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
|
|||
def FLT_S : FPCmpS_rr<0b001, "flt.s">;
|
||||
def FLE_S : FPCmpS_rr<0b000, "fle.s">;
|
||||
|
||||
def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s"> {
|
||||
def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
|
||||
Sched<[WriteFClass32, ReadFClass32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
|
||||
def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w"> {
|
||||
def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
|
||||
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>;
|
||||
|
||||
def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu"> {
|
||||
def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">,
|
||||
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
|
||||
let rs2 = 0b00001;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>;
|
||||
|
||||
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> {
|
||||
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">,
|
||||
Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> {
|
||||
let rs2 = 0b00000;
|
||||
}
|
||||
} // Predicates = [HasStdExtF]
|
||||
|
||||
let Predicates = [HasStdExtF, IsRV64] in {
|
||||
def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> {
|
||||
def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">,
|
||||
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>;
|
||||
|
||||
def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s"> {
|
||||
def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">,
|
||||
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
|
||||
let rs2 = 0b00011;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>;
|
||||
|
||||
def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l"> {
|
||||
def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">,
|
||||
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
|
||||
let rs2 = 0b00010;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>;
|
||||
|
||||
def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu"> {
|
||||
def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">,
|
||||
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
|
||||
let rs2 = 0b00011;
|
||||
}
|
||||
def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
|
||||
|
|
|
|||
|
|
@ -24,22 +24,35 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDTIntBinOp>;
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Predicates = [HasStdExtM] in {
|
||||
def MUL : ALU_rr<0b0000001, 0b000, "mul">;
|
||||
def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
|
||||
def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
|
||||
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
|
||||
def DIV : ALU_rr<0b0000001, 0b100, "div">;
|
||||
def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
|
||||
def REM : ALU_rr<0b0000001, 0b110, "rem">;
|
||||
def REMU : ALU_rr<0b0000001, 0b111, "remu">;
|
||||
def MUL : ALU_rr<0b0000001, 0b000, "mul">,
|
||||
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
||||
def MULH : ALU_rr<0b0000001, 0b001, "mulh">,
|
||||
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
||||
def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
|
||||
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
||||
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
|
||||
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
|
||||
def DIV : ALU_rr<0b0000001, 0b100, "div">,
|
||||
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
||||
def DIVU : ALU_rr<0b0000001, 0b101, "divu">,
|
||||
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
||||
def REM : ALU_rr<0b0000001, 0b110, "rem">,
|
||||
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
||||
def REMU : ALU_rr<0b0000001, 0b111, "remu">,
|
||||
Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
|
||||
} // Predicates = [HasStdExtM]
|
||||
|
||||
let Predicates = [HasStdExtM, IsRV64] in {
|
||||
def MULW : ALUW_rr<0b0000001, 0b000, "mulw">;
|
||||
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">;
|
||||
def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">;
|
||||
def REMW : ALUW_rr<0b0000001, 0b110, "remw">;
|
||||
def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">;
|
||||
def MULW : ALUW_rr<0b0000001, 0b000, "mulw">,
|
||||
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
|
||||
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
|
||||
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
||||
def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
|
||||
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
||||
def REMW : ALUW_rr<0b0000001, 0b110, "remw">,
|
||||
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
||||
def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
|
||||
Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
|
||||
} // Predicates = [HasStdExtM, IsRV64]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -0,0 +1,213 @@
|
|||
//==- RISCVSchedRocket32.td - Rocket Scheduling Definitions -*- tablegen -*-=//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// ===---------------------------------------------------------------------===//
|
||||
// The following definitions describe the simpler per-operand machine model.
|
||||
// This works with MachineScheduler. See MCSchedule.h for details.
|
||||
|
||||
// Rocket machine model for scheduling and other instruction cost heuristics.
|
||||
def Rocket32Model : SchedMachineModel {
|
||||
let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
|
||||
let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
|
||||
let LoadLatency = 3;
|
||||
let MispredictPenalty = 3;
|
||||
let CompleteModel = 1;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define each kind of processor resource and number available.
|
||||
|
||||
// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
|
||||
// Rocket is in-order.
|
||||
|
||||
let BufferSize = 0 in {
|
||||
def Rocket32UnitALU : ProcResource<1>; // Int ALU
|
||||
def Rocket32UnitIMul : ProcResource<1>; // Int Multiply
|
||||
def Rocket32UnitMem : ProcResource<1>; // Load/Store
|
||||
def Rocket32UnitB : ProcResource<1>; // Branch
|
||||
|
||||
def Rocket32UnitFPALU : ProcResource<1>; // FP ALU
|
||||
}
|
||||
|
||||
let BufferSize = 1 in {
|
||||
def Rocket32UnitIDiv : ProcResource<1>; // Int Division
|
||||
def Rocket32UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt'
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedWrite types which both map the ProcResources and
|
||||
// set the latency.
|
||||
|
||||
let SchedModel = Rocket32Model in {
|
||||
|
||||
def : WriteRes<WriteJmp, [Rocket32UnitB]>;
|
||||
def : WriteRes<WriteJal, [Rocket32UnitB]>;
|
||||
def : WriteRes<WriteJalr, [Rocket32UnitB]>;
|
||||
def : WriteRes<WriteJmpReg, [Rocket32UnitB]>;
|
||||
|
||||
def : WriteRes<WriteIALU, [Rocket32UnitALU]>;
|
||||
def : WriteRes<WriteShift, [Rocket32UnitALU]>;
|
||||
|
||||
// Multiplies on Rocket differ by implementation; placeholder until
|
||||
// we can determine how to read from command line
|
||||
def : WriteRes<WriteIMul, [Rocket32UnitIMul]> { let Latency = 4; }
|
||||
|
||||
// 32-bit divides have worse case latency of 34 cycle
|
||||
def : WriteRes<WriteIDiv, [Rocket32UnitIDiv]> {
|
||||
let Latency = 34;
|
||||
let ResourceCycles = [34];
|
||||
}
|
||||
|
||||
// Memory
|
||||
def : WriteRes<WriteSTB, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteSTH, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteSTW, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteFST32, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteFST64, [Rocket32UnitMem]>;
|
||||
|
||||
let Latency = 3 in {
|
||||
def : WriteRes<WriteLDB, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteLDH, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteCSR, [Rocket32UnitALU]>;
|
||||
}
|
||||
|
||||
let Latency = 2 in {
|
||||
def : WriteRes<WriteLDW, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteFLD32, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteFLD64, [Rocket32UnitMem]>;
|
||||
|
||||
def : WriteRes<WriteAtomicW, [Rocket32UnitMem]>;
|
||||
def : WriteRes<WriteAtomicLDW, [Rocket32UnitMem]>;
|
||||
}
|
||||
|
||||
def : WriteRes<WriteAtomicSTW, [Rocket32UnitMem]>;
|
||||
|
||||
// Most FP single precision operations are 4 cycles
|
||||
def : WriteRes<WriteFALU32, [Rocket32UnitFPALU]> { let Latency = 4; }
|
||||
|
||||
// Most FP double precision operations are 6 cycles
|
||||
def : WriteRes<WriteFALU64, [Rocket32UnitFPALU]> { let Latency = 6; }
|
||||
|
||||
let Latency = 2 in {
|
||||
def : WriteRes<WriteFCvtI32ToF32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtI32ToF64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF32ToI32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF64ToI32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF32ToF64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF64ToF32, [Rocket32UnitFPALU]>;
|
||||
|
||||
def : WriteRes<WriteFClass32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFClass64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCmp32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCmp64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovF32ToI32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovI32ToF32, [Rocket32UnitFPALU]>;
|
||||
}
|
||||
|
||||
let Latency = 5 in {
|
||||
def : WriteRes<WriteFMul32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulAdd32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulSub32, [Rocket32UnitFPALU]>;
|
||||
}
|
||||
|
||||
let Latency = 7 in {
|
||||
def : WriteRes<WriteFMul64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulAdd64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulSub64, [Rocket32UnitFPALU]>;
|
||||
}
|
||||
|
||||
// FP Divide unit on Rocket is not pipelined, so set resource cycles to latency
|
||||
let Latency = 20, ResourceCycles = [20] in {
|
||||
def : WriteRes<WriteFDiv32, [Rocket32UnitFPDivSqrt]>;
|
||||
def : WriteRes<WriteFDiv64, [Rocket32UnitFPDivSqrt]>;
|
||||
}
|
||||
|
||||
// FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency
|
||||
def : WriteRes<WriteFSqrt32, [Rocket32UnitFPDivSqrt]> { let Latency = 20;
|
||||
let ResourceCycles = [20];}
|
||||
def : WriteRes<WriteFSqrt64, [Rocket32UnitFPDivSqrt]> { let Latency = 25;
|
||||
let ResourceCycles = [25];}
|
||||
|
||||
def : WriteRes<WriteNop, []>;
|
||||
|
||||
def : InstRW<[WriteIALU], (instrs COPY)>;
|
||||
|
||||
let Unsupported = 1 in {
|
||||
def : WriteRes<WriteIALU32, []>;
|
||||
def : WriteRes<WriteShift32, []>;
|
||||
def : WriteRes<WriteIMul32, []>;
|
||||
def : WriteRes<WriteIDiv32, []>;
|
||||
def : WriteRes<WriteSTD, []>;
|
||||
def : WriteRes<WriteLDWU, []>;
|
||||
def : WriteRes<WriteLDD, []>;
|
||||
def : WriteRes<WriteAtomicD, []>;
|
||||
def : WriteRes<WriteAtomicLDD, []>;
|
||||
def : WriteRes<WriteAtomicSTD, []>;
|
||||
def : WriteRes<WriteFCvtI64ToF32, []>;
|
||||
def : WriteRes<WriteFCvtI64ToF64, []>;
|
||||
def : WriteRes<WriteFCvtF64ToI64, []>;
|
||||
def : WriteRes<WriteFCvtF32ToI64, []>;
|
||||
def : WriteRes<WriteFMovI64ToF64, []>;
|
||||
def : WriteRes<WriteFMovF64ToI64, []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedRead types with cycles.
|
||||
// Dummy definitions for RocketCore.
|
||||
def : ReadAdvance<ReadJmp, 0>;
|
||||
def : ReadAdvance<ReadJalr, 0>;
|
||||
def : ReadAdvance<ReadCSR, 0>;
|
||||
def : ReadAdvance<ReadStoreData, 0>;
|
||||
def : ReadAdvance<ReadMemBase, 0>;
|
||||
def : ReadAdvance<ReadIALU, 0>;
|
||||
def : ReadAdvance<ReadIALU32, 0>;
|
||||
def : ReadAdvance<ReadShift, 0>;
|
||||
def : ReadAdvance<ReadShift32, 0>;
|
||||
def : ReadAdvance<ReadIDiv, 0>;
|
||||
def : ReadAdvance<ReadIDiv32, 0>;
|
||||
def : ReadAdvance<ReadIMul, 0>;
|
||||
def : ReadAdvance<ReadIMul32, 0>;
|
||||
def : ReadAdvance<ReadAtomicWA, 0>;
|
||||
def : ReadAdvance<ReadAtomicWD, 0>;
|
||||
def : ReadAdvance<ReadAtomicDA, 0>;
|
||||
def : ReadAdvance<ReadAtomicDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDW, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTW, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTD, 0>;
|
||||
def : ReadAdvance<ReadFALU32, 0>;
|
||||
def : ReadAdvance<ReadFALU64, 0>;
|
||||
def : ReadAdvance<ReadFMul32, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd32, 0>;
|
||||
def : ReadAdvance<ReadFMulSub32, 0>;
|
||||
def : ReadAdvance<ReadFMul64, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd64, 0>;
|
||||
def : ReadAdvance<ReadFMulSub64, 0>;
|
||||
def : ReadAdvance<ReadFDiv32, 0>;
|
||||
def : ReadAdvance<ReadFDiv64, 0>;
|
||||
def : ReadAdvance<ReadFSqrt32, 0>;
|
||||
def : ReadAdvance<ReadFSqrt64, 0>;
|
||||
def : ReadAdvance<ReadFCmp32, 0>;
|
||||
def : ReadAdvance<ReadFCmp64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFMovI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFMovI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFClass32, 0>;
|
||||
def : ReadAdvance<ReadFClass64, 0>;
|
||||
}
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
//==- RISCVSchedRocket64.td - Rocket Scheduling Definitions -*- tablegen -*-=//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// ===---------------------------------------------------------------------===//
|
||||
// The following definitions describe the simpler per-operand machine model.
|
||||
// This works with MachineScheduler. See MCSchedule.h for details.
|
||||
|
||||
// Rocket machine model for scheduling and other instruction cost heuristics.
|
||||
def Rocket64Model : SchedMachineModel {
|
||||
let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
|
||||
let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
|
||||
let LoadLatency = 3;
|
||||
let MispredictPenalty = 3;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define each kind of processor resource and number available.
|
||||
|
||||
// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
|
||||
// Rocket is in-order.
|
||||
|
||||
let BufferSize = 0 in {
|
||||
def Rocket64UnitALU : ProcResource<1>; // Int ALU
|
||||
def Rocket64UnitIMul : ProcResource<1>; // Int Multiply
|
||||
def Rocket64UnitMem : ProcResource<1>; // Load/Store
|
||||
def Rocket64UnitB : ProcResource<1>; // Branch
|
||||
|
||||
def Rocket64UnitFPALU : ProcResource<1>; // FP ALU
|
||||
}
|
||||
|
||||
let BufferSize = 1 in {
|
||||
def Rocket64UnitIDiv : ProcResource<1>; // Int Division
|
||||
def Rocket64UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedWrite types which both map the ProcResources and
|
||||
// set the latency.
|
||||
|
||||
let SchedModel = Rocket64Model in {
|
||||
|
||||
def : WriteRes<WriteJmp, [Rocket64UnitB]>;
|
||||
def : WriteRes<WriteJal, [Rocket64UnitB]>;
|
||||
def : WriteRes<WriteJalr, [Rocket64UnitB]>;
|
||||
def : WriteRes<WriteJmpReg, [Rocket64UnitB]>;
|
||||
|
||||
def : WriteRes<WriteIALU32, [Rocket64UnitALU]>;
|
||||
def : WriteRes<WriteIALU, [Rocket64UnitALU]>;
|
||||
def : WriteRes<WriteShift32, [Rocket64UnitALU]>;
|
||||
def : WriteRes<WriteShift, [Rocket64UnitALU]>;
|
||||
|
||||
let Latency = 4 in {
|
||||
def : WriteRes<WriteIMul, [Rocket64UnitIMul]>;
|
||||
def : WriteRes<WriteIMul32, [Rocket64UnitIMul]>;
|
||||
}
|
||||
|
||||
// Integer divide varies based on operand magnitude and sign; worse case latency is 34.
|
||||
def : WriteRes<WriteIDiv32, [Rocket64UnitIDiv]> {
|
||||
let Latency = 34;
|
||||
let ResourceCycles = [34];
|
||||
}
|
||||
def : WriteRes<WriteIDiv, [Rocket64UnitIDiv]> {
|
||||
let Latency = 33;
|
||||
let ResourceCycles = [33];
|
||||
}
|
||||
|
||||
// Memory
|
||||
def : WriteRes<WriteSTB, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteSTH, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteSTW, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteSTD, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteFST32, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteFST64, [Rocket64UnitMem]>;
|
||||
|
||||
let Latency = 3 in {
|
||||
def : WriteRes<WriteLDB, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteLDH, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteCSR, [Rocket64UnitALU]>;
|
||||
}
|
||||
|
||||
let Latency = 2 in {
|
||||
def : WriteRes<WriteLDW, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteLDWU, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteLDD, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteFLD32, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteFLD64, [Rocket64UnitMem]>;
|
||||
|
||||
def : WriteRes<WriteAtomicW, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteAtomicD, [Rocket64UnitMem]>;
|
||||
|
||||
def : WriteRes<WriteAtomicLDW, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteAtomicLDD, [Rocket64UnitMem]>;
|
||||
}
|
||||
|
||||
def : WriteRes<WriteAtomicSTW, [Rocket64UnitMem]>;
|
||||
def : WriteRes<WriteAtomicSTD, [Rocket64UnitMem]>;
|
||||
|
||||
// Most FP single precision operations are 4 cycles
|
||||
def : WriteRes<WriteFALU32, [Rocket64UnitFPALU]> { let Latency = 4; }
|
||||
|
||||
// Most FP double precision operations are 6 cycles
|
||||
def : WriteRes<WriteFALU64, [Rocket64UnitFPALU]> { let Latency = 6; }
|
||||
|
||||
// Conversion instructions
|
||||
let Latency = 2 in {
|
||||
def : WriteRes<WriteFCvtI32ToF32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtI32ToF64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtI64ToF32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtI64ToF64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF32ToI32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF32ToI64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF64ToI32, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF64ToI64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF32ToF64, [Rocket32UnitFPALU]>;
|
||||
def : WriteRes<WriteFCvtF64ToF32, [Rocket32UnitFPALU]>;
|
||||
|
||||
def : WriteRes<WriteFClass32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFClass64, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFCmp32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFCmp64, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovF32ToI32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovI32ToF32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovF64ToI64, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMovI64ToF64, [Rocket64UnitFPALU]>;
|
||||
}
|
||||
|
||||
let Latency = 5 in {
|
||||
def : WriteRes<WriteFMul32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulAdd32, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulSub32, [Rocket64UnitFPALU]>;
|
||||
}
|
||||
|
||||
let Latency = 7 in {
|
||||
def : WriteRes<WriteFMul64, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulAdd64, [Rocket64UnitFPALU]>;
|
||||
def : WriteRes<WriteFMulSub64, [Rocket64UnitFPALU]>;
|
||||
}
|
||||
|
||||
// FP Divide unit on Rocket is not pipelined, so set resource cycles to latency
|
||||
let Latency = 20, ResourceCycles = [20] in {
|
||||
def : WriteRes<WriteFDiv32, [Rocket64UnitFPDivSqrt]>;
|
||||
def : WriteRes<WriteFDiv64, [Rocket64UnitFPDivSqrt]>;
|
||||
}
|
||||
|
||||
// FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency
|
||||
def : WriteRes<WriteFSqrt32, [Rocket64UnitFPDivSqrt]> { let Latency = 20;
|
||||
let ResourceCycles = [20]; }
|
||||
def : WriteRes<WriteFSqrt64, [Rocket64UnitFPDivSqrt]> { let Latency = 25;
|
||||
let ResourceCycles = [25]; }
|
||||
|
||||
def : WriteRes<WriteNop, []>;
|
||||
|
||||
def : InstRW<[WriteIALU], (instrs COPY)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedRead types with cycles.
|
||||
// Dummy definitions for RocketCore.
|
||||
def : ReadAdvance<ReadJmp, 0>;
|
||||
def : ReadAdvance<ReadJalr, 0>;
|
||||
def : ReadAdvance<ReadCSR, 0>;
|
||||
def : ReadAdvance<ReadStoreData, 0>;
|
||||
def : ReadAdvance<ReadMemBase, 0>;
|
||||
def : ReadAdvance<ReadIALU, 0>;
|
||||
def : ReadAdvance<ReadIALU32, 0>;
|
||||
def : ReadAdvance<ReadShift, 0>;
|
||||
def : ReadAdvance<ReadShift32, 0>;
|
||||
def : ReadAdvance<ReadIDiv, 0>;
|
||||
def : ReadAdvance<ReadIDiv32, 0>;
|
||||
def : ReadAdvance<ReadIMul, 0>;
|
||||
def : ReadAdvance<ReadIMul32, 0>;
|
||||
def : ReadAdvance<ReadAtomicWA, 0>;
|
||||
def : ReadAdvance<ReadAtomicWD, 0>;
|
||||
def : ReadAdvance<ReadAtomicDA, 0>;
|
||||
def : ReadAdvance<ReadAtomicDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDW, 0>;
|
||||
def : ReadAdvance<ReadAtomicLDD, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTW, 0>;
|
||||
def : ReadAdvance<ReadAtomicSTD, 0>;
|
||||
def : ReadAdvance<ReadFALU32, 0>;
|
||||
def : ReadAdvance<ReadFALU64, 0>;
|
||||
def : ReadAdvance<ReadFMul32, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd32, 0>;
|
||||
def : ReadAdvance<ReadFMulSub32, 0>;
|
||||
def : ReadAdvance<ReadFMul64, 0>;
|
||||
def : ReadAdvance<ReadFMulAdd64, 0>;
|
||||
def : ReadAdvance<ReadFMulSub64, 0>;
|
||||
def : ReadAdvance<ReadFDiv32, 0>;
|
||||
def : ReadAdvance<ReadFDiv64, 0>;
|
||||
def : ReadAdvance<ReadFSqrt32, 0>;
|
||||
def : ReadAdvance<ReadFSqrt64, 0>;
|
||||
def : ReadAdvance<ReadFCmp32, 0>;
|
||||
def : ReadAdvance<ReadFCmp64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI32, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFCvtI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF32ToF64, 0>;
|
||||
def : ReadAdvance<ReadFCvtF64ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF32ToI32, 0>;
|
||||
def : ReadAdvance<ReadFMovI32ToF32, 0>;
|
||||
def : ReadAdvance<ReadFMovF64ToI64, 0>;
|
||||
def : ReadAdvance<ReadFMovI64ToF64, 0>;
|
||||
def : ReadAdvance<ReadFClass32, 0>;
|
||||
def : ReadAdvance<ReadFClass64, 0>;
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
//===-- RISCVSchedule.td - RISCV Scheduling Definitions -------*- tablegen -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// Define scheduler resources associated with def operands.
|
||||
def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
|
||||
def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
|
||||
def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
|
||||
def WriteShift : SchedWrite; // 32 or 64-bit shift operations
|
||||
def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
|
||||
def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
|
||||
def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
|
||||
def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
|
||||
def WriteJmp : SchedWrite; // Jump
|
||||
def WriteJal : SchedWrite; // Jump and link
|
||||
def WriteJalr : SchedWrite; // Jump and link register
|
||||
def WriteJmpReg : SchedWrite; // Jump register
|
||||
def WriteNop : SchedWrite;
|
||||
def WriteLDB : SchedWrite; // Load byte
|
||||
def WriteLDH : SchedWrite; // Load half-word
|
||||
def WriteLDW : SchedWrite; // Load word
|
||||
def WriteLDWU : SchedWrite; // Load word unsigned
|
||||
def WriteLDD : SchedWrite; // Load double-word
|
||||
def WriteCSR : SchedWrite; // CSR instructions
|
||||
def WriteSTB : SchedWrite; // Store byte
|
||||
def WriteSTH : SchedWrite; // Store half-word
|
||||
def WriteSTW : SchedWrite; // Store word
|
||||
def WriteSTD : SchedWrite; // Store double-word
|
||||
def WriteAtomicW : SchedWrite; //Atomic memory operation word size
|
||||
def WriteAtomicD : SchedWrite; //Atomic memory operation double word size
|
||||
def WriteAtomicLDW : SchedWrite; // Atomic load word
|
||||
def WriteAtomicLDD : SchedWrite; // Atomic load double word
|
||||
def WriteAtomicSTW : SchedWrite; // Atomic store word
|
||||
def WriteAtomicSTD : SchedWrite; // Atomic store double word
|
||||
def WriteFALU32 : SchedWrite; // FP 32-bit computation
|
||||
def WriteFALU64 : SchedWrite; // FP 64-bit computation
|
||||
def WriteFMul32 : SchedWrite; // 32-bit floating point multiply
|
||||
def WriteFMulAdd32 : SchedWrite; // 32-bit floating point multiply add
|
||||
def WriteFMulSub32 : SchedWrite; // 32-bit floating point multiply sub
|
||||
def WriteFMul64 : SchedWrite; // 64-bit floating point multiply
|
||||
def WriteFMulAdd64 : SchedWrite; // 64-bit floating point multiply add
|
||||
def WriteFMulSub64 : SchedWrite; // 64-bit floating point multiply sub
|
||||
def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
|
||||
def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
|
||||
def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt
|
||||
def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt
|
||||
|
||||
// Integer to float conversions
|
||||
def WriteFCvtI32ToF32 : SchedWrite;
|
||||
def WriteFCvtI32ToF64 : SchedWrite;
|
||||
def WriteFCvtI64ToF32 : SchedWrite; // RV64I only
|
||||
def WriteFCvtI64ToF64 : SchedWrite; // RV64I only
|
||||
|
||||
//Float to integer conversions
|
||||
def WriteFCvtF32ToI32 : SchedWrite;
|
||||
def WriteFCvtF32ToI64 : SchedWrite; // RV64I only
|
||||
def WriteFCvtF64ToI32 : SchedWrite;
|
||||
def WriteFCvtF64ToI64 : SchedWrite; // RV64I only
|
||||
|
||||
// Float to float conversions
|
||||
def WriteFCvtF32ToF64 : SchedWrite;
|
||||
def WriteFCvtF64ToF32 : SchedWrite;
|
||||
|
||||
def WriteFConv32 : SchedWrite; // 32-bit floating point convert
|
||||
def WriteFConv64 : SchedWrite; // 64-bit floating point convert
|
||||
def WriteFClass32 : SchedWrite; // 32-bit floating point classify
|
||||
def WriteFClass64 : SchedWrite; // 64-bit floating point classify
|
||||
def WriteFCmp32 : SchedWrite; // 32-bit floating point compare
|
||||
def WriteFCmp64 : SchedWrite; // 64-bit floating point compare
|
||||
|
||||
def WriteFMovF32ToI32 : SchedWrite;
|
||||
def WriteFMovI32ToF32 : SchedWrite;
|
||||
def WriteFMovF64ToI64 : SchedWrite; // RV64I only
|
||||
def WriteFMovI64ToF64 : SchedWrite; // RV64I only
|
||||
|
||||
def WriteFMov32 : SchedWrite; // 32-bit floating point move
|
||||
def WriteFMov64 : SchedWrite; // 64-bit floating point move
|
||||
def WriteFLD32 : SchedWrite; // Floating point sp load
|
||||
def WriteFLD64 : SchedWrite; // Floating point dp load
|
||||
def WriteFST32 : SchedWrite; // Floating point sp store
|
||||
def WriteFST64 : SchedWrite; // Floating point dp store
|
||||
|
||||
/// Define scheduler resources associated with use operands.
|
||||
def ReadJmp : SchedRead;
|
||||
def ReadJalr : SchedRead;
|
||||
def ReadCSR : SchedRead;
|
||||
def ReadMemBase : SchedRead;
|
||||
def ReadStoreData : SchedRead;
|
||||
def ReadIALU : SchedRead;
|
||||
def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
|
||||
def ReadShift : SchedRead;
|
||||
def ReadShift32 : SchedRead; // 32-bit shift operations on RV64Ix
|
||||
def ReadIDiv : SchedRead;
|
||||
def ReadIDiv32 : SchedRead;
|
||||
def ReadIMul : SchedRead;
|
||||
def ReadIMul32 : SchedRead;
|
||||
def ReadAtomicWA : SchedRead;
|
||||
def ReadAtomicWD : SchedRead;
|
||||
def ReadAtomicDA : SchedRead;
|
||||
def ReadAtomicDD : SchedRead;
|
||||
def ReadAtomicLDW : SchedRead; // Atomic load word
|
||||
def ReadAtomicLDD : SchedRead; // Atomic load double word
|
||||
def ReadAtomicSTW : SchedRead; // Atomic store word
|
||||
def ReadAtomicSTD : SchedRead; // Atomic store double word
|
||||
def ReadFALU32 : SchedRead; // FP 32-bit computation
|
||||
def ReadFALU64 : SchedRead; // FP 64-bit computation
|
||||
def ReadFMul32 : SchedRead; // 32-bit floating point multiply
|
||||
def ReadFMulAdd32 : SchedRead; // 32-bit floating point multiply add
|
||||
def ReadFMulSub32 : SchedRead; // 32-bit floating point multiply sub
|
||||
def ReadFMul64 : SchedRead; // 64-bit floating point multiply
|
||||
def ReadFMulAdd64 : SchedRead; // 64-bit floating point multiply add
|
||||
def ReadFMulSub64 : SchedRead; // 64-bit floating point multiply sub
|
||||
def ReadFDiv32 : SchedRead; // 32-bit floating point divide
|
||||
def ReadFDiv64 : SchedRead; // 64-bit floating point divide
|
||||
def ReadFSqrt32 : SchedRead; // 32-bit floating point sqrt
|
||||
def ReadFSqrt64 : SchedRead; // 64-bit floating point sqrt
|
||||
def ReadFCmp32 : SchedRead;
|
||||
def ReadFCmp64 : SchedRead;
|
||||
def ReadFCvtF32ToI32 : SchedRead;
|
||||
def ReadFCvtF32ToI64 : SchedRead;
|
||||
def ReadFCvtF64ToI32 : SchedRead;
|
||||
def ReadFCvtF64ToI64 : SchedRead;
|
||||
def ReadFCvtI32ToF32 : SchedRead;
|
||||
def ReadFCvtI32ToF64 : SchedRead;
|
||||
def ReadFCvtI64ToF32 : SchedRead;
|
||||
def ReadFCvtI64ToF64 : SchedRead;
|
||||
def ReadFMovF32ToI32 : SchedRead;
|
||||
def ReadFMovI32ToF32 : SchedRead;
|
||||
def ReadFMovF64ToI64 : SchedRead;
|
||||
def ReadFMovI64ToF64 : SchedRead;
|
||||
def ReadFCvtF32ToF64 : SchedRead;
|
||||
def ReadFCvtF64ToF32 : SchedRead;
|
||||
def ReadFClass32 : SchedRead;
|
||||
def ReadFClass64 : SchedRead;
|
||||
Loading…
Reference in New Issue