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Move MOTy::UseType enum into MachineOperand. This eliminates the 

switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715
This commit is contained in:
Alkis Evlogimenos 2004-02-22 19:23:26 +00:00
parent 84b406650e
commit 8358cc573d
10 changed files with 168 additions and 156 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

143
llvm/include/llvm/CodeGen/MachineInstr.h
View File

@ -33,21 +33,6 @@ template <typename T> class ilist;
typedef short MachineOpCode;
//===----------------------------------------------------------------------===//
/// MOTy - MachineOperandType - This namespace contains an enum that describes
/// how the machine operand is used by the instruction: is it read, defined, or
/// both? Note that the MachineInstr/Operator class currently uses bool
/// arguments to represent this information instead of an enum. Eventually this
/// should change over to use this _easier to read_ representation instead.
///
namespace MOTy {
enum UseType {
Use, /// This machine operand is only read by the instruction
Def, /// This machine operand is only written by the instruction
UseAndDef /// This machine operand is read AND written
};
}
//===----------------------------------------------------------------------===//
// class MachineOperand
//
@ -84,6 +69,31 @@ namespace MOTy {
//===----------------------------------------------------------------------===//
struct MachineOperand {
private:
// Bit fields of the flags variable used for different operand properties
enum {
DEFFLAG = 0x01, // this is a def of the operand
USEFLAG = 0x02, // this is a use of the operand
HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
};
public:
// UseType - This enum describes how the machine operand is used by
// the instruction. Note that the MachineInstr/Operator class
// currently uses bool arguments to represent this information
// instead of an enum. Eventually this should change over to use
// this _easier to read_ representation instead.
//
enum UseType {
Use = USEFLAG, /// only read
Def = DEFFLAG, /// only written
UseAndDef = Use | Def /// read AND written
};
enum MachineOperandType {
MO_VirtualRegister, // virtual register for *value
MO_MachineRegister, // pre-assigned machine register `regNum'
@ -98,18 +108,6 @@ struct MachineOperand {
MO_GlobalAddress, // Address of a global value
};
private:
// Bit fields of the flags variable used for different operand properties
enum {
DEFFLAG = 0x01, // this is a def of the operand
USEFLAG = 0x02, // this is a use of the operand
HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
};
private:
union {
Value* value; // BasicBlockVal for a label operand.
@ -136,32 +134,19 @@ private:
opType(OpTy),
regNum(-1) {}
MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
: immedVal(0),
opType(OpTy),
regNum(Reg) {
switch (UseTy) {
case MOTy::Use: flags = USEFLAG; break;
case MOTy::Def: flags = DEFFLAG; break;
case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
default: assert(0 && "Invalid value for UseTy!");
}
}
MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy)
: immedVal(0), flags(UseTy), opType(OpTy), regNum(Reg) { }
MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
bool isPCRelative = false)
: value(V), opType(OpTy), regNum(-1) {
switch (UseTy) {
case MOTy::Use: flags = USEFLAG; break;
case MOTy::Def: flags = DEFFLAG; break;
case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
default: assert(0 && "Invalid value for UseTy!");
}
if (isPCRelative) flags |= PCRELATIVE;
: value(V),
flags(UseTy | (isPCRelative ? PCRELATIVE : 0)),
opType(OpTy),
regNum(-1) {
}
MachineOperand(MachineBasicBlock *mbb)
: MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
: MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) { }
MachineOperand(const std::string &SymName, bool isPCRelative)
: SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
@ -199,9 +184,8 @@ public:
/// getUseType - Returns the MachineOperandUseType of this operand.
///
MOTy::UseType getUseType() const {
return isUse() & isDef() ? MOTy::UseAndDef :
(isUse() ? MOTy::Use : MOTy::Def);
UseType getUseType() const {
return UseType(flags & (USEFLAG|DEFFLAG));
}
/// isPCRelative - This returns the value of the PCRELATIVE flag, which
@ -461,19 +445,24 @@ public:
void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
!isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
operands.push_back(
MachineOperand(V, MachineOperand::MO_VirtualRegister,
!isDef ? MachineOperand::Use :
(isDefAndUse ? MachineOperand::UseAndDef :
MachineOperand::Def)));
}
void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
bool isPCRelative = false) {
void addRegOperand(Value *V,
MachineOperand::UseType UTy = MachineOperand::Use,
bool isPCRelative = false) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
UTy, isPCRelative));
}
void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
void addCCRegOperand(Value *V,
MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
@ -486,17 +475,19 @@ public:
void addRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
isDef ? MOTy::Def : MOTy::Use));
operands.push_back(
MachineOperand(reg, MachineOperand::MO_VirtualRegister,
isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addRegOperand - Add a symbolic virtual register reference...
///
void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
void addRegOperand(int reg,
MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
UTy));
operands.push_back(
MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
}
/// addPCDispOperand - Add a PC relative displacement operand to the MI
@ -504,8 +495,8 @@ public:
void addPCDispOperand(Value *V) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
MOTy::Use));
operands.push_back(
MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
@ -513,17 +504,19 @@ public:
void addMachineRegOperand(int reg, bool isDef) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
isDef ? MOTy::Def : MOTy::Use));
operands.push_back(
MachineOperand(reg, MachineOperand::MO_MachineRegister,
isDef ? MachineOperand::Def : MachineOperand::Use));
}
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
///
void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
void addMachineRegOperand(int reg,
MachineOperand::UseType UTy = MachineOperand::Use) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
UTy));
operands.push_back(
MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
}
/// addZeroExtImmOperand - Add a zero extended constant argument to the
@ -532,8 +525,8 @@ public:
void addZeroExtImmOperand(int64_t intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(intValue,
MachineOperand::MO_UnextendedImmed));
operands.push_back(
MachineOperand(intValue, MachineOperand::MO_UnextendedImmed));
}
/// addSignExtImmOperand - Add a zero extended constant argument to the
@ -542,8 +535,8 @@ public:
void addSignExtImmOperand(int64_t intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand(intValue,
MachineOperand::MO_SignExtendedImmed));
operands.push_back(
MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed));
}
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
@ -572,9 +565,9 @@ public:
void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(MachineOperand((Value*)GV,
MachineOperand::MO_GlobalAddress,
MOTy::Use, isPCRelative));
operands.push_back(
MachineOperand((Value*)GV, MachineOperand::MO_GlobalAddress,
MachineOperand::Use, isPCRelative));
}
/// addExternalSymbolOperand - Add an external symbol operand to this instr

37
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -38,33 +38,36 @@ public:
/// addReg - Add a new virtual register operand...
///
const MachineInstrBuilder &addReg(int RegNo,
MOTy::UseType Ty = MOTy::Use) const {
const MachineInstrBuilder &addReg(
int RegNo,
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(RegNo, Ty);
return *this;
}
/// addReg - Add an LLVM value that is to be used as a register...
///
const MachineInstrBuilder &addReg(Value *V,
MOTy::UseType Ty = MOTy::Use) const {
const MachineInstrBuilder &addReg(
Value *V,
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addRegOperand(V, Ty);
return *this;
}
/// addReg - Add an LLVM value that is to be used as a register...
///
const MachineInstrBuilder &addCCReg(Value *V,
MOTy::UseType Ty = MOTy::Use) const {
const MachineInstrBuilder &addCCReg(
Value *V,
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addCCRegOperand(V, Ty);
return *this;
}
/// addRegDef - Add an LLVM value that is to be defined as a register... this
/// is the same as addReg(V, MOTy::Def).
/// is the same as addReg(V, MachineOperand::Def).
///
const MachineInstrBuilder &addRegDef(Value *V) const {
return addReg(V, MOTy::Def);
return addReg(V, MachineOperand::Def);
}
/// addPCDisp - Add an LLVM value to be treated as a PC relative
@ -77,8 +80,9 @@ public:
/// addMReg - Add a machine register operand...
///
const MachineInstrBuilder &addMReg(int Reg,
MOTy::UseType Ty = MOTy::Use) const {
const MachineInstrBuilder &addMReg(
int Reg,
MachineOperand::UseType Ty = MachineOperand::Use) const {
MI->addMachineRegOperand(Reg, Ty);
return *this;
}
@ -137,9 +141,10 @@ inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) {
/// destination virtual register. NumOperands is the number of additional add*
/// calls that are expected, it does not include the destination register.
///
inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands,
unsigned DestReg,
MOTy::UseType useType = MOTy::Def) {
inline MachineInstrBuilder BuildMI(
int Opcode, unsigned NumOperands,
unsigned DestReg,
MachineOperand::UseType useType = MachineOperand::Def) {
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1,
true, true)).addReg(DestReg, useType);
}
@ -160,9 +165,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
unsigned NumOperands, unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(BB, Opcode,
NumOperands+1)).addReg(DestReg,
MOTy::Def);
return MachineInstrBuilder(
new MachineInstr(BB, Opcode, NumOperands+1))
.addReg(DestReg, MachineOperand::Def);
}
} // End llvm namespace

14
llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
View File

@ -74,7 +74,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
int SP = TM.getRegInfo().getStackPointer();
if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) {
mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C)
.addMReg(SP, MOTy::Def));
.addMReg(SP, MachineOperand::Def));
} else {
// We have to put the stack size value into a register before SAVE.
// Use register %g1 since it is volatile across calls. Note that the
@ -86,21 +86,22 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
SparcIntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
.addMReg(uregNum, MOTy::Def);
.addMReg(uregNum, MachineOperand::Def);
M->setOperandHi32(0);
mvec.push_back(M);
M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
.addMReg(uregNum, MOTy::Def);
.addMReg(uregNum, MachineOperand::Def);
M->setOperandLo32(1);
mvec.push_back(M);
M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
.addMReg(uregNum, MOTy::Def);
.addMReg(uregNum, MachineOperand::Def);
mvec.push_back(M);
// Now generate the SAVE using the value in register %g1
M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def);
M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
.addMReg(SP,MachineOperand::Def);
mvec.push_back(M);
}
@ -148,7 +149,8 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
int ZR = TM.getRegInfo().getZeroRegNum();
MachineInstr *Restore =
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
.addMReg(ZR, MachineOperand::Def);
MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst);

59
llvm/lib/Target/Sparc/SparcInstrSelection.cpp
View File

@ -786,9 +786,9 @@ CreateShiftInstructions(const TargetMachine& target,
MachineInstr* M = (optArgVal2 != NULL)
? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
.addReg(shiftDest, MOTy::Def)
.addReg(shiftDest, MachineOperand::Def)
: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
.addReg(shiftDest, MOTy::Def);
.addReg(shiftDest, MachineOperand::Def);
mvec.push_back(M);
if (shiftDest != destVal) {
@ -1119,11 +1119,11 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
// Instruction 2: andn tmpProd, 0x0f -> tmpAndn
getMvec.push_back(BuildMI(V9::ADDi, 3).addReg(tmpProd).addSImm(15)
.addReg(tmpAdd15, MOTy::Def));
.addReg(tmpAdd15, MachineOperand::Def));
// Instruction 3: add tmpAndn, 0x10 -> tmpAdd16
getMvec.push_back(BuildMI(V9::ANDi, 3).addReg(tmpAdd15).addSImm(-16)
.addReg(tmpAndf0, MOTy::Def));
.addReg(tmpAndf0, MachineOperand::Def));
totalSizeVal = tmpAndf0;
}
@ -1141,7 +1141,7 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
// Instruction 2: sub %sp, totalSizeVal -> %sp
getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
.addMReg(SPReg,MOTy::Def));
.addMReg(SPReg,MachineOperand::Def));
// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
@ -1534,7 +1534,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
MachineInstr* retMI =
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
.addMReg(target.getRegInfo().getZeroRegNum(), MOTy::Def);
.addMReg(target.getRegInfo().getZeroRegNum(), MachineOperand::Def);
// If there is a value to return, we need to:
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
@ -1581,11 +1581,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
.addReg(retValToUse).addReg(retVReg, MOTy::Def));
.addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(retType), 3)
.addReg(retValToUse).addSImm((int64_t) 0)
.addReg(retVReg, MOTy::Def));
.addReg(retVReg, MachineOperand::Def));
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, retRegNum);
@ -1751,7 +1751,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
mvec.push_back(BuildMI(V9::MOVRZi, 3).addReg(notArg).addZImm(1)
.addReg(notI, MOTy::UseAndDef));
.addReg(notI, MachineOperand::UseAndDef));
break;
}
@ -1786,7 +1786,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// value will be retained if the condition is false.
MachineOpCode opCode = foldCase? V9::MOVRZi : V9::MOVRNZi;
mvec.push_back(BuildMI(opCode, 3).addReg(opVal).addZImm(1)
.addReg(castI, MOTy::UseAndDef));
.addReg(castI, MachineOperand::UseAndDef));
break;
}
@ -2149,12 +2149,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value *lhs = subtreeRoot->leftChild()->getValue();
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def));
.addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef));
.addReg(dest, MachineOperand::UseAndDef));
}
break;
@ -2180,12 +2180,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def));
.addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef));
.addReg(dest, MachineOperand::UseAndDef));
}
break;
@ -2210,12 +2210,12 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value *lhs = subtreeRoot->leftChild()->getValue();
Value *dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
.addReg(dest, MOTy::Def));
.addReg(dest, MachineOperand::Def));
if (notArg->getType() == Type::BoolTy) {
// set 1 in result register if result of above is non-zero
mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
.addReg(dest, MOTy::UseAndDef));
.addReg(dest, MachineOperand::UseAndDef));
}
break;
}
@ -2262,7 +2262,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
mvec.push_back(BuildMI(movOpCode, 3)
.addReg(subtreeRoot->leftChild()->getValue())
.addZImm(1).addReg(setCCInstr, MOTy::UseAndDef));
.addZImm(1)
.addReg(setCCInstr, MachineOperand::UseAndDef));
break;
}
@ -2336,12 +2337,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
mvec.push_back(BuildMI(V9::SUBccr, 4)
.addReg(leftOpToUse)
.addReg(rightOpToUse)
.addMReg(target.getRegInfo().getZeroRegNum(),MOTy::Def)
.addCCReg(tmpForCC, MOTy::Def));
.addMReg(target.getRegInfo()
.getZeroRegNum(), MachineOperand::Def)
.addCCReg(tmpForCC, MachineOperand::Def));
} else {
// FP condition: dest of FCMP should be some FCCn register
mvec.push_back(BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
.addCCReg(tmpForCC, MOTy::Def)
.addCCReg(tmpForCC, MachineOperand::Def)
.addReg(leftOpToUse)
.addReg(rightOpToUse));
}
@ -2359,7 +2361,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
M = (BuildMI(movOpCode, 3).addCCReg(tmpForCC).addZImm(1)
.addReg(setCCInstr, MOTy::UseAndDef));
.addReg(setCCInstr, MachineOperand::UseAndDef));
mvec.push_back(M);
}
break;
@ -2589,7 +2591,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
.addMReg(regInfo.getFramePointer()).addSImm(tmpOffset)
.addReg(argVReg, MOTy::Def);
.addReg(argVReg, MachineOperand::Def);
// Mark operand with register it should be assigned
// both for copy and for the callMI
@ -2668,11 +2670,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// -- For non-FP values, create an add-with-0 instruction
if (argType->isFloatingPoint())
M=(BuildMI(argType==Type::FloatTy? V9::FMOVS :V9::FMOVD,2)
.addReg(argVal).addReg(argVReg, MOTy::Def));
.addReg(argVal).addReg(argVReg, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(argType), 3)
.addReg(argVal).addSImm((int64_t) 0)
.addReg(argVReg, MOTy::Def));
.addReg(argVReg, MachineOperand::Def));
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
@ -2716,11 +2718,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// -- For non-FP values, create an add-with-0 instruction
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
.addReg(retVReg).addReg(callInstr, MOTy::Def));
.addReg(retVReg).addReg(callInstr, MachineOperand::Def));
else
M = (BuildMI(ChooseAddInstructionByType(retType), 3)
.addReg(retVReg).addSImm((int64_t) 0)
.addReg(callInstr, MOTy::Def));
.addReg(callInstr, MachineOperand::Def));
// Mark the operand with the register it should be assigned
// Also mark the implicit ref of the call defining this operand
@ -2878,12 +2880,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
tmpI, NULL, "maskHi2");
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpI)
.addZImm(8*(4-destSize))
.addReg(srlArgToUse, MOTy::Def));
.addReg(srlArgToUse, MachineOperand::Def));
}
// Logical right shift 32-N to get zero extension in top 64-N bits.
mvec.push_back(BuildMI(V9::SRLi5, 3).addReg(srlArgToUse)
.addZImm(8*(4-destSize)).addReg(dest, MOTy::Def));
.addZImm(8*(4-destSize))
.addReg(dest, MachineOperand::Def));
} else if (destSize < 8) {
assert(0 && "Unsupported type size: 32 < size < 64 bits");

45
llvm/lib/Target/Sparc/SparcRegInfo.cpp
View File

@ -699,7 +699,7 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
MI = (BuildMI(V9::RDCCR, 2)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr))
.addMReg(DestReg,MOTy::Def));
.addMReg(DestReg,MachineOperand::Def));
} else {
// copy int reg to intCC reg
assert(getRegType(SrcReg) == IntRegType
@ -708,7 +708,8 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
.addMReg(SrcReg)
.addMReg(SparcIntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr), MOTy::Def));
SparcIntCCRegClass::ccr),
MachineOperand::Def));
}
break;
@ -718,15 +719,17 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
.addMReg(DestReg, MOTy::Def);
.addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
.addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
.addMReg(DestReg, MachineOperand::Def);
break;
default:
@ -800,7 +803,7 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
MI = (BuildMI(V9::RDCCR, 2)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr))
.addMReg(scratchReg, MOTy::Def));
.addMReg(scratchReg, MachineOperand::Def));
mvec.push_back(MI);
cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
@ -860,29 +863,29 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
switch (RegType) {
case IntRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
MOTy::Def);
MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
MOTy::Def);
MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
.addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
MOTy::Def);
MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
MOTy::Def);
MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
.addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
MOTy::Def);
MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
MOTy::Def);
MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
.addMReg(DestReg, MachineOperand::Def);
break;
case IntCCRegType:
@ -893,7 +896,7 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
.addMReg(scratchReg)
.addMReg(SparcIntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr), MOTy::Def));
SparcIntCCRegClass::ccr), MachineOperand::Def));
break;
case FloatCCRegType: {
@ -901,10 +904,10 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
SparcSpecialRegClass::fsr);
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(fsrRegNum, MOTy::UseAndDef);
.addMReg(fsrRegNum, MachineOperand::UseAndDef);
else
MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
.addMReg(fsrRegNum, MOTy::UseAndDef);
.addMReg(fsrRegNum, MachineOperand::UseAndDef);
break;
}
default:

2
llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
View File

@ -422,7 +422,7 @@ uint64_t JITResolver::emitStubForFunction(Function *F) {
// restore %g0, 0, %g0
MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
.addMReg(g0, MOTy::Def);
.addMReg(g0, MachineOperand::Def);
SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*R));
delete R;

2
llvm/lib/Target/X86/InstSelectSimple.cpp
View File

@ -43,7 +43,7 @@ inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
MBB->insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
}
/// BMI - A special BuildMI variant that takes an iterator to insert the

3
llvm/lib/Target/X86/PeepholeOptimizer.cpp
View File

@ -149,7 +149,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
}
unsigned R0 = MI->getOperand(0).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef)
.addZImm((char)Val));
return true;
}
}

4
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -29,8 +29,8 @@ X86InstrInfo::X86InstrInfo()
// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
//
MachineInstr* X86InstrInfo::createNOPinstr() const {
return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
.addReg(X86::AX, MOTy::UseAndDef);
return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MachineOperand::UseAndDef)
.addReg(X86::AX, MachineOperand::UseAndDef);
}

15
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -295,10 +295,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
New=BuildMI(X86::SUBri32, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(Amount);
} else {
assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
New=BuildMI(X86::ADDri32, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(Amount);
}
// Replace the pseudo instruction with a new instruction...
@ -360,7 +362,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(NumBytes);
MBB.insert(MBBI, MI);
}
@ -396,7 +399,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
if (NumBytes) {
// adjust stack pointer: ESP -= numbytes
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(NumBytes);
MBB.insert(MBBI, MI);
}
}
@ -427,7 +431,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
unsigned NumBytes = MFI->getStackSize();
if (NumBytes) { // adjust stack pointer back: ESP += numbytes
MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
MI =BuildMI(X86::ADDri32, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(NumBytes);
MBB.insert(MBBI, MI);
}
}