forked from OSchip/llvm-project
[X86][AVX] Add 256-bit vector horizontal op redundant shuffle tests
llvm-svn: 337558
This commit is contained in:
Simon Pilgrim
parent
cccd21d42c
commit
8342126c4e
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@ -1,6 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; The next 8 tests check for matching the horizontal op and eliminating the shuffle.
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; PR34111 - https://bugs.llvm.org/show_bug.cgi?id=34111
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@ -22,6 +23,55 @@ define <4 x float> @hadd_v4f32(<4 x float> %a) {
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ret <4 x float> %shuf
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}
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define <8 x float> @hadd_v8f32a(<8 x float> %a) {
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; SSSE3-LABEL: hadd_v8f32a:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movaps %xmm0, %xmm2
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; SSSE3-NEXT: haddps %xmm1, %xmm2
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0]
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; SSSE3-NEXT: movaps %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hadd_v8f32a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vhaddps %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hadd_v8f32a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vhaddps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,2,1]
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; AVX2-NEXT: retq
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%a0 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a1 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%hop = fadd <4 x float> %a0, %a1
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%shuf = shufflevector <4 x float> %hop, <4 x float> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3>
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ret <8 x float> %shuf
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}
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define <8 x float> @hadd_v8f32b(<8 x float> %a) {
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; SSSE3-LABEL: hadd_v8f32b:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: haddps %xmm0, %xmm0
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; SSSE3-NEXT: haddps %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v8f32b:
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; AVX: # %bb.0:
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; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX-NEXT: retq
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%a0 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
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%a1 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
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%hop = fadd <8 x float> %a0, %a1
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%shuf = shufflevector <8 x float> %hop, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
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ret <8 x float> %shuf
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}
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define <4 x float> @hsub_v4f32(<4 x float> %a) {
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; SSSE3-LABEL: hsub_v4f32:
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; SSSE3: # %bb.0:
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@ -39,6 +89,55 @@ define <4 x float> @hsub_v4f32(<4 x float> %a) {
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ret <4 x float> %shuf
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}
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define <8 x float> @hsub_v8f32a(<8 x float> %a) {
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; SSSE3-LABEL: hsub_v8f32a:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movaps %xmm0, %xmm2
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; SSSE3-NEXT: hsubps %xmm1, %xmm2
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0]
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; SSSE3-NEXT: movaps %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hsub_v8f32a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vhsubps %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hsub_v8f32a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vhsubps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,2,1]
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; AVX2-NEXT: retq
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%a0 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a1 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%hop = fsub <4 x float> %a0, %a1
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%shuf = shufflevector <4 x float> %hop, <4 x float> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3>
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ret <8 x float> %shuf
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}
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define <8 x float> @hsub_v8f32b(<8 x float> %a) {
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; SSSE3-LABEL: hsub_v8f32b:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: hsubps %xmm0, %xmm0
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; SSSE3-NEXT: hsubps %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v8f32b:
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; AVX: # %bb.0:
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; AVX-NEXT: vhsubps %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX-NEXT: retq
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%a0 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
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%a1 = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
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%hop = fsub <8 x float> %a0, %a1
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%shuf = shufflevector <8 x float> %hop, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
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ret <8 x float> %shuf
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}
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define <2 x double> @hadd_v2f64(<2 x double> %a) {
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; SSSE3-LABEL: hadd_v2f64:
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; SSSE3: # %bb.0:
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@ -56,6 +155,25 @@ define <2 x double> @hadd_v2f64(<2 x double> %a) {
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ret <2 x double> %shuf
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}
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define <4 x double> @hadd_v4f64(<4 x double> %a) {
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; SSSE3-LABEL: hadd_v4f64:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: haddpd %xmm0, %xmm0
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; SSSE3-NEXT: haddpd %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vhaddpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX-NEXT: retq
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%a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
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%a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
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%hop = fadd <4 x double> %a0, %a1
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%shuf = shufflevector <4 x double> %hop, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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ret <4 x double> %shuf
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}
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define <2 x double> @hsub_v2f64(<2 x double> %a) {
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; SSSE3-LABEL: hsub_v2f64:
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; SSSE3: # %bb.0:
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@ -73,6 +191,25 @@ define <2 x double> @hsub_v2f64(<2 x double> %a) {
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ret <2 x double> %shuf
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}
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define <4 x double> @hsub_v4f64(<4 x double> %a) {
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; SSSE3-LABEL: hsub_v4f64:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: hsubpd %xmm0, %xmm0
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; SSSE3-NEXT: hsubpd %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vhsubpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX-NEXT: retq
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%a0 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
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%a1 = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
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%hop = fsub <4 x double> %a0, %a1
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%shuf = shufflevector <4 x double> %hop, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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ret <4 x double> %shuf
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}
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define <4 x i32> @hadd_v4i32(<4 x i32> %a) {
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; SSSE3-LABEL: hadd_v4i32:
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; SSSE3: # %bb.0:
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@ -90,6 +227,67 @@ define <4 x i32> @hadd_v4i32(<4 x i32> %a) {
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ret <4 x i32> %shuf
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}
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define <8 x i32> @hadd_v8i32a(<8 x i32> %a) {
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; SSSE3-LABEL: hadd_v8i32a:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movdqa %xmm0, %xmm2
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; SSSE3-NEXT: phaddd %xmm1, %xmm2
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,0,1]
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; SSSE3-NEXT: movdqa %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hadd_v8i32a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hadd_v8i32a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1]
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; AVX2-NEXT: retq
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%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%hop = add <4 x i32> %a0, %a1
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%shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3>
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ret <8 x i32> %shuf
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}
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define <8 x i32> @hadd_v8i32b(<8 x i32> %a) {
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; SSSE3-LABEL: hadd_v8i32b:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: phaddd %xmm0, %xmm0
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; SSSE3-NEXT: phaddd %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hadd_v8i32b:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm0[0,2,2,3,4,6,6,7]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,3,2,3,5,7,6,7]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
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; AVX1-NEXT: vpaddd %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hadd_v8i32b:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
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; AVX2-NEXT: retq
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%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
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%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
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%hop = add <8 x i32> %a0, %a1
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%shuf = shufflevector <8 x i32> %hop, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
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ret <8 x i32> %shuf
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}
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define <4 x i32> @hsub_v4i32(<4 x i32> %a) {
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; SSSE3-LABEL: hsub_v4i32:
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; SSSE3: # %bb.0:
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@ -107,6 +305,67 @@ define <4 x i32> @hsub_v4i32(<4 x i32> %a) {
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ret <4 x i32> %shuf
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}
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define <8 x i32> @hsub_v8i32a(<8 x i32> %a) {
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; SSSE3-LABEL: hsub_v8i32a:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movdqa %xmm0, %xmm2
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; SSSE3-NEXT: phsubd %xmm1, %xmm2
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,0,1]
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; SSSE3-NEXT: movdqa %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hsub_v8i32a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vphsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hsub_v8i32a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vphsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1]
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; AVX2-NEXT: retq
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%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%hop = sub <4 x i32> %a0, %a1
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%shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef, i32 2, i32 3>
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ret <8 x i32> %shuf
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}
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define <8 x i32> @hsub_v8i32b(<8 x i32> %a) {
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; SSSE3-LABEL: hsub_v8i32b:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: phsubd %xmm0, %xmm0
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; SSSE3-NEXT: phsubd %xmm1, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hsub_v8i32b:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpermilps {{.*#+}} ymm1 = ymm0[0,2,2,3,4,6,6,7]
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; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,3,2,3,5,7,6,7]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
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; AVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: hsub_v8i32b:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vphsubd %ymm0, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: retq
|
||||
%a0 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 4, i32 6, i32 undef, i32 undef>
|
||||
%a1 = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 5, i32 7, i32 undef, i32 undef>
|
||||
%hop = sub <8 x i32> %a0, %a1
|
||||
%shuf = shufflevector <8 x i32> %hop, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
|
||||
ret <8 x i32> %shuf
|
||||
}
|
||||
|
||||
define <8 x i16> @hadd_v8i16(<8 x i16> %a) {
|
||||
; SSSE3-LABEL: hadd_v8i16:
|
||||
; SSSE3: # %bb.0:
|
||||
|
|
|
|||
Loading…
Reference in New Issue