forked from OSchip/llvm-project
[DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalization
Improves commutation potential llvm-svn: 284113
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@ -863,6 +863,17 @@ static bool isOneConstantOrOneSplatConstant(SDValue N) {
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return false;
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return false;
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}
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}
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// Determines if it is a constant integer of all ones or a splatted vector of a
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// constant integer of all ones (with no undefs).
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// Do not permit build vector implicit truncation.
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static bool isAllOnesConstantOrAllOnesSplatConstant(SDValue N) {
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unsigned BitWidth = N.getScalarValueSizeInBits();
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if (ConstantSDNode *Splat = isConstOrConstSplat(N))
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return Splat->isAllOnesValue() &&
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Splat->getAPIntValue().getBitWidth() == BitWidth;
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return false;
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}
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SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
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SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
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SDValue N1) {
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SDValue N1) {
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EVT VT = N0.getValueType();
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EVT VT = N0.getValueType();
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@ -1938,7 +1949,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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}
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}
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// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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if (isAllOnesConstant(N0))
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if (isAllOnesConstantOrAllOnesSplatConstant(N0))
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return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
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return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
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// fold A-(A-B) -> B
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// fold A-(A-B) -> B
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@ -50,14 +50,13 @@ define <4 x i32> @combine_vec_sub_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sub_negone:
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; SSE-LABEL: combine_vec_sub_negone:
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; SSE: # BB#0:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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; SSE-NEXT: retq
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;
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;
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; AVX-LABEL: combine_vec_sub_negone:
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; AVX-LABEL: combine_vec_sub_negone:
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; AVX: # BB#0:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX-NEXT: retq
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%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
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%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
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ret <4 x i32> %1
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ret <4 x i32> %1
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