forked from OSchip/llvm-project
Switch ARM to using AltOrders instead of MethodBodies.
This slightly changes the GPR allocation order on Darwin where R9 is not a callee-saved register: Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11 After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11 llvm-svn: 133326
This commit is contained in:
Jakob Stoklund Olesen
parent
3337f7d50a
commit
831ae0105a
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@ -202,42 +202,14 @@ def FPEXC : ARMReg<8, "fpexc">;
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//
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def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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SP, LR, PC)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned ARM_GPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_GPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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GPRClass::iterator
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GPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO;
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return ARM_GPR_AO;
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}
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
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return ARM_GPR_AO + (sizeof(ARM_GPR_AO)/sizeof(unsigned));
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}
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// Allocate LR as the first CSR since it is always saved anyway.
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
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// know how to spill them. If we make our prologue/epilogue code smarter at
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// some point, we can go back to using the above allocation orders for the
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// Thumb1 instructions that know how to use hi regs.
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let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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}
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@ -246,44 +218,9 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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// or SP (R13 or R15) are used. The ARM ISA refers to these operands
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// via the BadReg() pseudo-code description.
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def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned ARM_rGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10,
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ARM::R11 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_rGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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rGPRClass::iterator
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rGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_rGPR_AO;
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return ARM_rGPR_AO;
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}
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rGPRClass::iterator
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rGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_rGPR_AO + (sizeof(THUMB_rGPR_AO)/sizeof(unsigned));
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return ARM_rGPR_AO + (sizeof(ARM_rGPR_AO)/sizeof(unsigned));
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}
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let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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}
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@ -296,52 +233,12 @@ def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
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// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
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// this class and the preceding one(!) This is what we want.
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def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// R9 is available.
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static const unsigned ARM_GPR_R9_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R9, ARM::R12 };
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// R9 is not available.
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static const unsigned ARM_GPR_NOR9_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_GPR_AO_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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tcGPRClass::iterator
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tcGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO_TC;
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return Subtarget.isTargetDarwin() ? ARM_GPR_R9_TC : ARM_GPR_NOR9_TC;
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}
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tcGPRClass::iterator
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tcGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
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return Subtarget.isTargetDarwin() ?
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ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)) :
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ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
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}
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let AltOrders = [(and tcGPR, tGPR)];
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let AltOrderSelect = [{
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return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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}
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// Scalar single precision floating point register class..
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def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>;
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@ -355,48 +252,9 @@ def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)>;
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// is double-word alignment though.
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def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
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(sequence "D%u", 0, 31)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// VFP2 / VFPv3-D16
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static const unsigned ARM_DPR_VFP2[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
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// VFP3: D8-D15 are callee saved and should be allocated last.
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// Save other low registers for use as DPR_VFP2 and DPR_8 classes.
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static const unsigned ARM_DPR_VFP3[] = {
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ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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ARM::D20, ARM::D21, ARM::D22, ARM::D23,
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ARM::D24, ARM::D25, ARM::D26, ARM::D27,
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ARM::D28, ARM::D29, ARM::D30, ARM::D31,
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
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DPRClass::iterator
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DPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3() && !Subtarget.hasD16())
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return ARM_DPR_VFP3;
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return ARM_DPR_VFP2;
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}
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DPRClass::iterator
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DPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3() && !Subtarget.hasD16())
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return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
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else
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return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
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}
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}];
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// Allocate non-VFP2 registers D16-D31 first.
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let AltOrders = [(rotl DPR, 16)];
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let AltOrderSelect = [{ return 1; }];
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}
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// Subset of DPR that are accessible with VFP2 (and so that also have
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@ -417,29 +275,9 @@ def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
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def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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(sequence "Q%u", 0, 15)> {
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let SubRegClasses = [(DPR dsub_0, dsub_1)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Q4-Q7 are callee saved and should be allocated last.
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// Save other low registers for use as QPR_VFP2 and QPR_8 classes.
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static const unsigned ARM_QPR[] = {
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ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
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ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
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ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
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ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
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QPRClass::iterator
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QPRClass::allocation_order_begin(const MachineFunction &MF) const {
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return ARM_QPR;
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}
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QPRClass::iterator
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QPRClass::allocation_order_end(const MachineFunction &MF) const {
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return ARM_QPR + (sizeof(ARM_QPR)/sizeof(unsigned));
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}
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}];
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// Allocate non-VFP2 aliases Q8-Q15 first.
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let AltOrders = [(rotl QPR, 8)];
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let AltOrderSelect = [{ return 1; }];
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}
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// Subset of QPR that have 32-bit SPR subregs.
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@ -461,27 +299,9 @@ def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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def QQPR : RegisterClass<"ARM", [v4i64], 256, (sequence "QQ%u", 0, 7)> {
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let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3),
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(QPR qsub_0, qsub_1)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// QQ2-QQ3 are callee saved and should be allocated last.
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// Save other low registers for use as QPR_VFP2 and QPR_8 classes.
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static const unsigned ARM_QQPR[] = {
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ARM::QQ4, ARM::QQ5, ARM::QQ6, ARM::QQ7,
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ARM::QQ0, ARM::QQ1, ARM::QQ2, ARM::QQ3 };
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QQPRClass::iterator
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QQPRClass::allocation_order_begin(const MachineFunction &MF) const {
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return ARM_QQPR;
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}
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QQPRClass::iterator
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QQPRClass::allocation_order_end(const MachineFunction &MF) const {
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return ARM_QQPR + (sizeof(ARM_QQPR)/sizeof(unsigned));
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}
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}];
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// Allocate non-VFP2 aliases first.
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let AltOrders = [(rotl QQPR, 4)];
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let AltOrderSelect = [{ return 1; }];
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}
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// Subset of QQPR that have 32-bit SPR subregs.
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@ -498,26 +318,9 @@ def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {
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let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,
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dsub_4, dsub_5, dsub_6, dsub_7),
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(QPR qsub_0, qsub_1, qsub_2, qsub_3)];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// QQQQ1 is callee saved and should be allocated last.
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// Save QQQQ0 for use as QPR_VFP2 and QPR_8 classes.
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static const unsigned ARM_QQQQPR[] = {
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ARM::QQQQ2, ARM::QQQQ3, ARM::QQQQ0, ARM::QQQQ1 };
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QQQQPRClass::iterator
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QQQQPRClass::allocation_order_begin(const MachineFunction &MF) const {
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return ARM_QQQQPR;
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}
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QQQQPRClass::iterator
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QQQQPRClass::allocation_order_end(const MachineFunction &MF) const {
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return ARM_QQQQPR + (sizeof(ARM_QQQQPR)/sizeof(unsigned));
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}
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}];
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// Allocate non-VFP2 aliases first.
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let AltOrders = [(rotl QQQQPR, 2)];
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let AltOrderSelect = [{ return 1; }];
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}
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// Condition code registers.
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@ -22,7 +22,7 @@
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define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
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entry:
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; CHECK: ldr.w {{(r[0-9]+)|(lr)}}, [r7, #28]
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; CHECK: ldr{{(.w)?}} {{(r[0-9]+)|(lr)}}, [r7, #28]
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%xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
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%ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
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br label %bb20
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