forked from OSchip/llvm-project
[AVX-512] Simplify code for creating 512-bit SHUF128 operations.
We don't need two loops and we can safely assume assume and hardcode the size of the widened mask. llvm-svn: 290942
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llvm/lib/Target/X86
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@ -12616,33 +12616,26 @@ static SDValue lowerV4X128VectorShuffle(const SDLoc &DL, MVT VT,
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
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}
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// Try to lower to to vshuf64x2/vshuf32x4.
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assert(WidenedMask.size() == 4);
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SDValue Ops[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT)};
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unsigned PermMask = 0;
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// Insure elements came from the same Op.
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int MaxOp1Index = VT.getVectorNumElements()/2 - 1;
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for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
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if (WidenedMask[i] == SM_SentinelZero)
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return SDValue();
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if (WidenedMask[i] == SM_SentinelUndef)
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for (int i = 0; i < 4; ++i) {
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assert(WidenedMask[i] >= -1);
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if (WidenedMask[i] < 0)
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continue;
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SDValue Op = WidenedMask[i] > MaxOp1Index ? V2 : V1;
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unsigned OpIndex = (i < Size/2) ? 0 : 1;
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SDValue Op = WidenedMask[i] >= 4 ? V2 : V1;
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unsigned OpIndex = i / 2;
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if (Ops[OpIndex].isUndef())
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Ops[OpIndex] = Op;
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else if (Ops[OpIndex] != Op)
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return SDValue();
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}
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// Form a 128-bit permutation.
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// Convert the 64-bit shuffle mask selection values into 128-bit selection
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// bits defined by a vshuf64x2 instruction's immediate control byte.
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unsigned PermMask = 0, Imm = 0;
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unsigned ControlBitsNum = WidenedMask.size() / 2;
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for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
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// Use first element in place of undef mask.
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Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
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PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
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// Convert the 128-bit shuffle mask selection values into 128-bit selection
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// bits defined by a vshuf64x2 instruction's immediate control byte.
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PermMask |= (WidenedMask[i] % 4) << (i * 2);
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}
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return DAG.getNode(X86ISD::SHUF128, DL, VT, Ops[0], Ops[1],
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