forked from OSchip/llvm-project
Add rlwnm instruction for variable rotate
Generate rotate left/right immediate Generate code for brcondtwoway Use new livein/liveout functionality llvm-svn: 21187
This commit is contained in:
Nate Begeman
parent
3a7f5768c5
commit
8309a333dd
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@ -16,7 +16,7 @@
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PowerPCInstrInfo.h"
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#include "PPC32RegisterInfo.h"
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#include "PPC32TargetMachine.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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@ -49,7 +49,6 @@ namespace {
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addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
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// PowerPC has no intrinsics for these particular operations
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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@ -129,6 +128,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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SDOperand newroot, argt;
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unsigned ObjSize;
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bool needsLoad = false;
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bool ArgLive = !I->use_empty();
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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@ -138,8 +138,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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case MVT::i16:
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case MVT::i32:
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ObjSize = 4;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx]);
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argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
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DAG.getRoot());
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if (ObjectVT != MVT::i32)
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@ -149,10 +150,11 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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}
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break;
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case MVT::i64: ObjSize = 8;
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if (!ArgLive) break;
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// FIXME: can split 64b load between reg/mem if it is last arg in regs
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if (GPR_remaining > 1) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
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MF.addLiveIn(GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx+1]);
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// Copy the extracted halves into the virtual registers
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SDOperand argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
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DAG.getRoot());
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@ -164,10 +166,12 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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needsLoad = true;
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}
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break;
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case MVT::f32: ObjSize = 4;
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case MVT::f64: ObjSize = 8;
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case MVT::f32:
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case MVT::f64:
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ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
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if (!ArgLive) break;
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if (FPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
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MF.addLiveIn(FPR[FPR_idx]);
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argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
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DAG.getRoot());
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--FPR_remaining;
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@ -214,7 +218,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// result of va_next.
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std::vector<SDOperand> MemOps;
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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MF.addLiveIn(GPR[GPR_idx]);
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SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, FIN);
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@ -226,6 +230,26 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
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}
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(PPC::R3);
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break;
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case MVT::i64:
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MF.addLiveOut(PPC::R3);
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MF.addLiveOut(PPC::R4);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(PPC::F1);
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break;
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}
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return ArgValues;
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}
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@ -440,7 +464,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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}
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namespace {
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Statistic<>NotLogic("ppc-codegen", "Number of inverted logical ops");
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Statistic<>Rotates("ppc-codegen", "Number of rotates emitted");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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@ -837,6 +861,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
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/// 3. or shr, and 7. or shr, shl
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/// 4. or and, shr
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bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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bool IsRotate = false;
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unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
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unsigned Op0Opc = OR.getOperand(0).getOpcode();
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unsigned Op1Opc = OR.getOperand(1).getOpcode();
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@ -865,12 +890,14 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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switch(Op1Opc) {
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case ISD::SHL:
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Amount = CN->getValue();
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InsMask <<= Amount;
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InsMask <<= Amount;
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if (Op0Opc == ISD::SRL) IsRotate = true;
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break;
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case ISD::SRL:
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Amount = CN->getValue();
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InsMask >>= Amount;
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Amount = 32-Amount;
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if (Op0Opc == ISD::SHL) IsRotate = true;
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break;
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case ISD::AND:
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InsMask &= (unsigned)CN->getValue();
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@ -887,6 +914,16 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
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unsigned MB, ME;
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if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && IsRunOfOnes(InsMask, MB, ME)) {
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unsigned Tmp1, Tmp2;
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// Check for rotlwi / rotrwi here, a special case of bitfield insert
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// where both bitfield halves are sourced from the same value.
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if (IsRotate &&
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OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
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++Rotates; // Statistic
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Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
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.addImm(0).addImm(31);
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return true;
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}
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if (Op0Opc == ISD::AND)
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Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
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else
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@ -954,26 +991,38 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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void ISel::SelectBranchCC(SDOperand N)
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{
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assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
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// Get the MBB we will fall through to so that we can hand it off to the
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// branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
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//ilist<MachineBasicBlock>::iterator It = BB;
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//MachineBasicBlock *Fallthrough = ++It;
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Select(N.getOperand(0)); //chain
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unsigned Opc = SelectSetCR0(N.getOperand(1));
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// FIXME: Use this once we have something approximating two-way branches
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// We cannot currently use this in case the ISel hands us something like
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// BRcc MBBx
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// BR MBBy
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// since the fallthrough basic block for the conditional branch does not start
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// with the unconditional branch (it is skipped over).
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//BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
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// .addMBB(Dest).addMBB(Fallthrough);
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BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
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// Iterate to the next basic block, unless we're already at the end of the
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ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
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if (It != E) ++It;
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// If this is a two way branch, then grab the fallthrough basic block argument
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// and build a PowerPC branch pseudo-op, suitable for long branch conversion
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// if necessary by the branch selection pass. Otherwise, emit a standard
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// conditional branch.
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if (N.getOpcode() == ISD::BRCONDTWOWAY) {
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MachineBasicBlock *Fallthrough =
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cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
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if (Dest != It) {
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BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
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.addMBB(Dest).addMBB(Fallthrough);
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if (Fallthrough != It)
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BuildMI(BB, PPC::B, 1).addMBB(Fallthrough);
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} else {
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if (Fallthrough != It) {
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Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
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BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
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.addMBB(Fallthrough).addMBB(Dest);
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}
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}
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} else {
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BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
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}
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return;
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}
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@ -1670,7 +1719,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (N.getOperand(0).getOpcode() == ISD::XOR &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue()) {
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++NotLogic;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
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@ -1679,7 +1727,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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// Check for NOT, NOR, and NAND: xor (copy, or, and), -1
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue()) {
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++NotLogic;
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switch(N.getOperand(0).getOpcode()) {
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case ISD::OR:
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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@ -2145,6 +2192,7 @@ void ISel::Select(SDOperand N) {
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return;
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}
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case ISD::BRCOND:
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case ISD::BRCONDTWOWAY:
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SelectBranchCC(N);
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return;
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case ISD::CopyToReg:
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@ -458,7 +458,9 @@ def RLWIMI : MForm_2<20, 0, 0, 0,
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def RLWINM : MForm_2<21, 0, 0, 0,
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(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
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"rlwinm $rA, $rS, $SH, $MB, $ME">;
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def RLWNM : MForm_2<23, 0, 0, 0,
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(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
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"rlwnm $rA, $rS, $rB, $MB, $ME">;
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// MD-Form instructions. 64 bit rotate instructions.
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//
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