forked from OSchip/llvm-project
[Hexagon] Dropping old combine instructions without encodings.
llvm-svn: 224992
This commit is contained in:
Colin LeMahieu
parent
377ac65340
commit
82fb8cba16
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@ -570,7 +570,7 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
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return;
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}
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if (LoOperand.isGlobal()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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@ -588,7 +588,7 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
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if (!isUInt<6>(LoOperand.getImm())) {
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assert(isInt<8>(HiOperand.getImm()));
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addImm(LoOperand.getImm());
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return;
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@ -613,7 +613,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
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// Handle global.
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if (HiOperand.isGlobal()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
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HiOperand.getTargetFlags())
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.addReg(LoReg, LoRegKillFlag);
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@ -621,7 +621,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
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}
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// Insert new combine instruction.
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// DoubleRegDest = combine #HiImm, LoReg
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addReg(LoReg, LoRegKillFlag);
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}
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@ -638,7 +638,7 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
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// Handle global.
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if (LoOperand.isGlobal()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
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.addReg(HiReg, HiRegKillFlag)
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.addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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@ -647,7 +647,7 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
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// Insert new combine instruction.
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// DoubleRegDest = combine HiReg, #LoImm
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
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.addReg(HiReg, HiRegKillFlag)
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.addImm(LoOperand.getImm());
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}
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@ -257,50 +257,6 @@ def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU32/PERM +
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//===----------------------------------------------------------------------===//
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// Combine
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// Rdd=combine(Rs, #s8)
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
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hasSideEffects = 0, validSubTargets = HasV4SubT in
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def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, s8Ext:$src2),
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"$dst = combine($src1, #$src2)",
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[]>,
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Requires<[HasV4T]>;
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// Rdd=combine(#s8, Rs)
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
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hasSideEffects = 0, validSubTargets = HasV4SubT in
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def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
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(ins s8Ext:$src1, IntRegs:$src2),
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"$dst = combine(#$src1, $src2)",
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[]>,
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Requires<[HasV4T]>;
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def HexagonWrapperCombineRI_V4 :
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SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
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def HexagonWrapperCombineIR_V4 :
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SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
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def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
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(COMBINE_rI_V4 IntRegs:$r, s8ExtPred:$i)>,
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Requires<[HasV4T]>;
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def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
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(COMBINE_Ir_V4 s8ExtPred:$i, IntRegs:$r)>,
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Requires<[HasV4T]>;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
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hasSideEffects = 0, validSubTargets = HasV4SubT in
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def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
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(ins s8Imm:$src1, u6Ext:$src2),
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"$dst = combine(#$src1, #$src2)",
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[]>,
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Requires<[HasV4T]>;
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//===----------------------------------------------------------------------===//
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// ALU32/PERM +
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//===----------------------------------------------------------------------===//
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@ -331,6 +287,39 @@ let opExtendable = 1, isCodeGenOnly = 0 in
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def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
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"$Rdd = combine(#$s8, $Rs)">;
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def HexagonWrapperCombineRI_V4 :
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SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
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def HexagonWrapperCombineIR_V4 :
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SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
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def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
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(A4_combineri IntRegs:$r, s8ExtPred:$i)>,
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Requires<[HasV4T]>;
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def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
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(A4_combineir s8ExtPred:$i, IntRegs:$r)>,
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Requires<[HasV4T]>;
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// A4_combineii: Set two small immediates.
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let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
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def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
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"$Rdd = combine(#$s8, #$U6)"> {
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bits<5> Rdd;
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bits<8> s8;
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bits<6> U6;
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let IClass = 0b0111;
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let Inst{27-23} = 0b11001;
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let Inst{20-16} = U6{5-1};
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let Inst{13} = U6{0};
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let Inst{12-5} = s8;
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let Inst{4-0} = Rdd;
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}
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//===----------------------------------------------------------------------===//
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// ALU32/PERM -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LD +
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//===----------------------------------------------------------------------===//
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@ -502,80 +491,80 @@ def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
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// zext i1->i64
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def : Pat <(i64 (zext (i1 PredRegs:$src1))),
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(i64 (COMBINE_Ir_V4 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
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(i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
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Requires<[HasV4T]>;
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// zext i32->i64
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def : Pat <(i64 (zext (i32 IntRegs:$src1))),
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(i64 (COMBINE_Ir_V4 0, (i32 IntRegs:$src1)))>,
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(i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
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Requires<[HasV4T]>;
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// zext i8->i64
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def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrub_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
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s11_0ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// zext i1->i64
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def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
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s11_0ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrub_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
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s11_0ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// zext i16->i64
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def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
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s11_1ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadruh_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
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s11_1ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// anyext i16->i64
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def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
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s11_1ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadrh_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
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s11_1ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// zext i32->i64
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def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 100 in
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def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
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s11_2ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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// anyext i32->i64
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def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
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(i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,
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(i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 100 in
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def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
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(i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,
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(i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
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s11_2ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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@ -3329,11 +3318,11 @@ def STriw_offset_ext_V4 : STInst<(outs),
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Requires<[HasV4T]>;
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def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
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(i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
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(i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
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Requires<[HasV4T]>;
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def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
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(i64 (COMBINE_Ir_V4 (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
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(i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
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Requires<[HasV4T]>;
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@ -3342,19 +3331,19 @@ def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
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// zextloadi8.
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let Predicates = [HasV4T], AddedComplexity = 120 in {
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def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
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(i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
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def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
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(i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
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def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>;
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def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
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(i64 (COMBINE_Ir_V4 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
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(i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
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def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
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(i64 (COMBINE_Ir_V4 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
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(i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
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def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
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(i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
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@ -3364,11 +3353,11 @@ def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
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// zextloadi16.
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let AddedComplexity = 120 in {
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def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
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(i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
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(i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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@ -3376,11 +3365,11 @@ def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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Requires<[HasV4T]>;
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def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
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(i64 (COMBINE_Ir_V4 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
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(i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
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(i64 (COMBINE_Ir_V4 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
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(i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
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@ -3392,11 +3381,11 @@ def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
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// zextloadi32.
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let AddedComplexity = 120 in {
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def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
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(i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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(i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
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(i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
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Requires<[HasV4T]>;
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def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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@ -3404,11 +3393,11 @@ def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
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Requires<[HasV4T]>;
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def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
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(i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
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(i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
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Requires<[HasV4T]>;
|
||||
|
||||
def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
|
||||
(i64 (COMBINE_Ir_V4 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
|
||||
(i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
|
|||
// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
|
||||
// %vreg170:DoublRegs, %vreg169:IntRegs
|
||||
if (!DisableOptExtTo64 &&
|
||||
MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
|
||||
MI->getOpcode () == Hexagon::A4_combineir) {
|
||||
assert (MI->getNumOperands() == 3);
|
||||
MachineOperand &Dst = MI->getOperand(0);
|
||||
MachineOperand &Src1 = MI->getOperand(1);
|
||||
|
|
|
|||
Loading…
Reference in New Issue