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[X86] LowerBITCAST - pull out repeated calls to getOperand(0). NFCI. 

llvm-svn: 325695
This commit is contained in:
Simon Pilgrim 2018-02-21 16:35:40 +00:00
parent 352f92c8d6
commit 82d33b7c44
1 changed files with 7 additions and 8 deletions
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15
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -23703,7 +23703,8 @@ static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget &Subtarget,
static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget, static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) { SelectionDAG &DAG) {
MVT SrcVT = Op.getOperand(0).getSimpleValueType(); SDValue Src = Op.getOperand(0);
MVT SrcVT = Src.getSimpleValueType();
MVT DstVT = Op.getSimpleValueType(); MVT DstVT = Op.getSimpleValueType();
// Legalize (v64i1 (bitcast i64 (X))) by splitting the i64, bitcasting each // Legalize (v64i1 (bitcast i64 (X))) by splitting the i64, bitcasting each
@ -23711,12 +23712,11 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget,
if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) { if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) {
assert(!Subtarget.is64Bit() && "Expected 32-bit mode"); assert(!Subtarget.is64Bit() && "Expected 32-bit mode");
assert(Subtarget.hasBWI() && "Expected BWI target"); assert(Subtarget.hasBWI() && "Expected BWI target");
SDValue Op0 = Op->getOperand(0);
SDLoc dl(Op); SDLoc dl(Op);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Src,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0, dl));
Lo = DAG.getBitcast(MVT::v32i1, Lo); Lo = DAG.getBitcast(MVT::v32i1, Lo);
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Src,
DAG.getIntPtrConstant(1, dl)); DAG.getIntPtrConstant(1, dl));
Hi = DAG.getBitcast(MVT::v32i1, Hi); Hi = DAG.getBitcast(MVT::v32i1, Hi);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi); return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
@ -23729,7 +23729,6 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget,
// This conversion needs to be expanded. // This conversion needs to be expanded.
return SDValue(); return SDValue();
SDValue Op0 = Op->getOperand(0);
SmallVector<SDValue, 16> Elts; SmallVector<SDValue, 16> Elts;
SDLoc dl(Op); SDLoc dl(Op);
unsigned NumElts; unsigned NumElts;
@ -23741,14 +23740,14 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget,
// Widen the vector in input in the case of MVT::v2i32. // Widen the vector in input in the case of MVT::v2i32.
// Example: from MVT::v2i32 to MVT::v4i32. // Example: from MVT::v2i32 to MVT::v4i32.
for (unsigned i = 0, e = NumElts; i != e; ++i) for (unsigned i = 0, e = NumElts; i != e; ++i)
Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, Op0, Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, Src,
DAG.getIntPtrConstant(i, dl))); DAG.getIntPtrConstant(i, dl)));
} else { } else {
assert(SrcVT == MVT::i64 && !Subtarget.is64Bit() && assert(SrcVT == MVT::i64 && !Subtarget.is64Bit() &&
"Unexpected source type in LowerBITCAST"); "Unexpected source type in LowerBITCAST");
Elts.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, Elts.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Src,
DAG.getIntPtrConstant(0, dl))); DAG.getIntPtrConstant(0, dl)));
Elts.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op0, Elts.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Src,
DAG.getIntPtrConstant(1, dl))); DAG.getIntPtrConstant(1, dl)));
NumElts = 2; NumElts = 2;
SVT = MVT::i32; SVT = MVT::i32;