forked from OSchip/llvm-project
[WebAssembly] Update relaxed SIMD opcodes and names
to reflect the latest state of the proposal: https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format. Moves code around to match the instruction order from the proposal, but the only functional changes are to the names and opcodes. Reviewed By: aheejin Differential Revision: https://reviews.llvm.org/D125726
This commit is contained in:
Thomas Lively
parent
bd9e46815d
commit
82a13d05ab
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@ -1334,7 +1334,37 @@ defm Q15MULR_SAT_S :
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SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>;
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//===----------------------------------------------------------------------===//
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// Fused Multiply- Add and Subtract (FMA/FMS)
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// Relaxed swizzle
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//===----------------------------------------------------------------------===//
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defm RELAXED_SWIZZLE :
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RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
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[(set (v16i8 V128:$dst),
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(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
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"i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 0x100>;
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//===----------------------------------------------------------------------===//
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// Relaxed floating-point to int conversions
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//===----------------------------------------------------------------------===//
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multiclass SIMD_RELAXED_CONVERT<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
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defm op#_#vec :
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RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
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[(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
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vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
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}
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_signed,
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"relaxed_trunc_f32x4_s", 0x101>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned,
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"relaxed_trunc_f32x4_u", 0x102>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero,
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"relaxed_trunc_f64x2_s_zero", 0x103>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero,
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"relaxed_trunc_f64x2_u_zero", 0x104>;
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//===----------------------------------------------------------------------===//
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// Relaxed Fused Multiply- Add and Subtract (FMA/FMS)
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//===----------------------------------------------------------------------===//
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multiclass SIMDFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
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@ -1342,16 +1372,18 @@ multiclass SIMDFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
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RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
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[(set (vec.vt V128:$dst), (int_wasm_fma
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(vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
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vec.prefix#".fma\t$dst, $a, $b, $c", vec.prefix#".fma", simdopA>;
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vec.prefix#".relaxed_fma\t$dst, $a, $b, $c",
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vec.prefix#".relaxed_fma", simdopA>;
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defm FMS_#vec :
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RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
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[(set (vec.vt V128:$dst), (int_wasm_fms
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(vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
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vec.prefix#".fms\t$dst, $a, $b, $c", vec.prefix#".fms", simdopS>;
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vec.prefix#".relaxed_fms\t$dst, $a, $b, $c",
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vec.prefix#".relaxed_fms", simdopS>;
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}
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defm "" : SIMDFM<F32x4, 0xaf, 0xb0>;
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defm "" : SIMDFM<F64x2, 0xcf, 0xd0>;
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defm "" : SIMDFM<F32x4, 0x105, 0x106>;
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defm "" : SIMDFM<F64x2, 0x107, 0x108>;
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//===----------------------------------------------------------------------===//
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// Laneselect
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@ -1362,25 +1394,16 @@ multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
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RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
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[(set (vec.vt V128:$dst), (int_wasm_laneselect
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(vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
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vec.prefix#".laneselect\t$dst, $a, $b, $c", vec.prefix#".laneselect", op>;
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vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
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vec.prefix#".relaxed_laneselect", op>;
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}
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defm "" : SIMDLANESELECT<I8x16, 0xb2>;
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defm "" : SIMDLANESELECT<I16x8, 0xb3>;
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defm "" : SIMDLANESELECT<I32x4, 0xd2>;
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defm "" : SIMDLANESELECT<I64x2, 0xd3>;
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defm "" : SIMDLANESELECT<I8x16, 0x109>;
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defm "" : SIMDLANESELECT<I16x8, 0x10a>;
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defm "" : SIMDLANESELECT<I32x4, 0x10b>;
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defm "" : SIMDLANESELECT<I64x2, 0x10c>;
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//===----------------------------------------------------------------------===//
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// Relaxed swizzle
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//===----------------------------------------------------------------------===//
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defm RELAXED_SWIZZLE :
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RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
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[(set (v16i8 V128:$dst),
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(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
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"i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
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//===----------------------------------------------------------------------===//
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// Relaxed floating-point min and max.
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//===----------------------------------------------------------------------===//
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@ -1398,22 +1421,5 @@ multiclass SIMD_RELAXED_FMINMAX<Vec vec, bits<32> simdopMin, bits<32> simdopMax>
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vec.prefix#".relaxed_max\t$dst, $a, $b", vec.prefix#".relaxed_max", simdopMax>;
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}
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defm "" : SIMD_RELAXED_FMINMAX<F32x4, 0xb4, 0xe2>;
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defm "" : SIMD_RELAXED_FMINMAX<F64x2, 0xd4, 0xee>;
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//===----------------------------------------------------------------------===//
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// Relaxed floating-point to int conversions
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//===----------------------------------------------------------------------===//
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multiclass SIMD_RELAXED_CONVERT<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
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defm op#_#vec :
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RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
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[(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
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vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
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}
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_signed, "relaxed_trunc_f32x4_s", 0xa5>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned, "relaxed_trunc_f32x4_u", 0xa6>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero, "relaxed_trunc_f64x2_s_zero", 0xc5>;
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defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero, "relaxed_trunc_f64x2_u_zero", 0xc6>;
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defm "" : SIMD_RELAXED_FMINMAX<F32x4, 0x10d, 0x10e>;
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defm "" : SIMD_RELAXED_FMINMAX<F64x2, 0x10f, 0x110>;
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@ -182,7 +182,7 @@ define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
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; CHECK-LABEL: laneselect_v16i8:
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; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i8x16.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
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define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
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@ -358,7 +358,7 @@ define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
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; CHECK-LABEL: laneselect_v8i16:
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; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i16x8.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
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define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
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@ -516,7 +516,7 @@ define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) {
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; CHECK-LABEL: laneselect_v4i32:
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; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i32x4.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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@ -615,7 +615,7 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
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; CHECK-LABEL: laneselect_v2i64:
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; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: i64x2.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: i64x2.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
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define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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@ -702,7 +702,7 @@ define <4 x float> @nearest_v4f32(<4 x float> %a) {
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; CHECK-LABEL: fma_v4f32:
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; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f32x4.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: f32x4.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
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define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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@ -714,7 +714,7 @@ define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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; CHECK-LABEL: fms_v4f32:
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; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f32x4.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: f32x4.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>)
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define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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@ -825,7 +825,7 @@ define <2 x double> @nearest_v2f64(<2 x double> %a) {
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; CHECK-LABEL: fma_v2f64:
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; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: f64x2.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
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define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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@ -837,7 +837,7 @@ define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c
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; CHECK-LABEL: fms_v2f64:
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; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}}
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; CHECK-NEXT: f64x2.fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: f64x2.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>)
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define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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@ -779,55 +779,59 @@ main:
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# CHECK: f64x2.convert_low_i32x4_u # encoding: [0xfd,0xff,0x01]
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f64x2.convert_low_i32x4_u
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# CHECK: f32x4.fma # encoding: [0xfd,0xaf,0x01]
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f32x4.fma
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# CHECK: f32x4.fms # encoding: [0xfd,0xb0,0x01]
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f32x4.fms
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# CHECK: f64x2.fma # encoding: [0xfd,0xcf,0x01]
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f64x2.fma
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# CHECK: f64x2.fms # encoding: [0xfd,0xd0,0x01]
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f64x2.fms
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# CHECK: i8x16.laneselect # encoding: [0xfd,0xb2,0x01]
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i8x16.laneselect
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# CHECK: i16x8.laneselect # encoding: [0xfd,0xb3,0x01]
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i16x8.laneselect
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# CHECK: i32x4.laneselect # encoding: [0xfd,0xd2,0x01]
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i32x4.laneselect
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# CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
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i64x2.laneselect
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# CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
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# CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0x80,0x02]
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i8x16.relaxed_swizzle
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# CHECK: f32x4.relaxed_min # encoding: [0xfd,0xb4,0x01]
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f32x4.relaxed_min
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# CHECK: f32x4.relaxed_max # encoding: [0xfd,0xe2,0x01]
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f32x4.relaxed_max
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# CHECK: f64x2.relaxed_min # encoding: [0xfd,0xd4,0x01]
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f64x2.relaxed_min
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# CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
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f64x2.relaxed_max
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# CHECK: i32x4.relaxed_trunc_f32x4_s # encoding: [0xfd,0xa5,0x01]
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# CHECK: i32x4.relaxed_trunc_f32x4_s # encoding: [0xfd,0x81,0x02]
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i32x4.relaxed_trunc_f32x4_s
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# CHECK: i32x4.relaxed_trunc_f32x4_u # encoding: [0xfd,0xa6,0x01]
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# CHECK: i32x4.relaxed_trunc_f32x4_u # encoding: [0xfd,0x82,0x02]
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i32x4.relaxed_trunc_f32x4_u
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# CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0xc5,0x01]
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# CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0x83,0x02]
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i32x4.relaxed_trunc_f64x2_s_zero
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# CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0xc6,0x01]
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# CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02]
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i32x4.relaxed_trunc_f64x2_u_zero
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# CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02]
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f32x4.relaxed_fma
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# CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02]
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f32x4.relaxed_fms
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# CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02]
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f64x2.relaxed_fma
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# CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02]
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f64x2.relaxed_fms
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# CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02]
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i8x16.relaxed_laneselect
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# CHECK: i16x8.relaxed_laneselect # encoding: [0xfd,0x8a,0x02]
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i16x8.relaxed_laneselect
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# CHECK: i32x4.relaxed_laneselect # encoding: [0xfd,0x8b,0x02]
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i32x4.relaxed_laneselect
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# CHECK: i64x2.relaxed_laneselect # encoding: [0xfd,0x8c,0x02]
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i64x2.relaxed_laneselect
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# CHECK: f32x4.relaxed_min # encoding: [0xfd,0x8d,0x02]
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f32x4.relaxed_min
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# CHECK: f32x4.relaxed_max # encoding: [0xfd,0x8e,0x02]
|
||||
f32x4.relaxed_max
|
||||
|
||||
# CHECK: f64x2.relaxed_min # encoding: [0xfd,0x8f,0x02]
|
||||
f64x2.relaxed_min
|
||||
|
||||
# CHECK: f64x2.relaxed_max # encoding: [0xfd,0x90,0x02]
|
||||
f64x2.relaxed_max
|
||||
|
||||
# TODO: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02]
|
||||
# TODO: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
|
||||
# TODO: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
|
||||
|
||||
end_function
|
||||
|
|
|
|||
Loading…
Reference in New Issue