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s/ARM::BRIND/ARM::BX/g to coincide with r120366. 

llvm-svn: 120371
This commit is contained in:
Bill Wendling 2010-11-30 00:48:15 +00:00
parent 90c4947df7
commit 8294a30d54
3 changed files with 5 additions and 5 deletions
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2
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1260,7 +1260,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
{ {
MCInst TmpInst; MCInst TmpInst;
TmpInst.setOpcode(ARM::BRIND); TmpInst.setOpcode(ARM::BX);
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
// Predicate. // Predicate.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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@ -434,7 +434,7 @@ bool isJumpTableBranchOpcode(int Opc) {
static inline static inline
bool isIndirectBranchOpcode(int Opc) { bool isIndirectBranchOpcode(int Opc) {
return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
} }
/// getInstrPredicate - If instruction is predicated, returns its predicate /// getInstrPredicate - If instruction is predicated, returns its predicate

6
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -790,7 +790,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Misc. Branch Instructions. // Misc. Branch Instructions.
// BLXr9, BXr9 // BLXr9, BXr9
// BRIND, BX_RET // BX, BX_RET
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -805,8 +805,8 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (Opcode == ARM::BX_RET) if (Opcode == ARM::BX_RET)
return true; return true;
// BLXr9 and BRIND take one GPR reg. // BLXr9 and BX take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) { if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected"); "Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,