forked from OSchip/llvm-project
Do not remove implicit defs in BranchFolder
Branch folder removes implicit defs if they are the only non-branching instructions in a block, and the branches do not use the defined registers. The problem is that in some cases these implicit defs are required for the liveness information to be correct. Differential Revision: https://reviews.llvm.org/D25478 llvm-svn: 284036
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@ -145,59 +145,6 @@ void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
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MLI->removeBlock(MBB);
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MLI->removeBlock(MBB);
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}
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}
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/// OptimizeImpDefsBlock - If a basic block is just a bunch of implicit_def
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/// followed by terminators, and if the implicitly defined registers are not
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/// used by the terminators, remove those implicit_def's. e.g.
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/// BB1:
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/// r0 = implicit_def
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/// r1 = implicit_def
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/// br
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/// This block can be optimized away later if the implicit instructions are
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/// removed.
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bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
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SmallSet<unsigned, 4> ImpDefRegs;
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MachineBasicBlock::iterator I = MBB->begin();
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while (I != MBB->end()) {
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if (!I->isImplicitDef())
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break;
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unsigned Reg = I->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
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SubRegs.isValid(); ++SubRegs)
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ImpDefRegs.insert(*SubRegs);
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} else {
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ImpDefRegs.insert(Reg);
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}
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++I;
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}
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if (ImpDefRegs.empty())
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return false;
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MachineBasicBlock::iterator FirstTerm = I;
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while (I != MBB->end()) {
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if (!TII->isUnpredicatedTerminator(*I))
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return false;
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// See if it uses any of the implicitly defined registers.
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for (const MachineOperand &MO : I->operands()) {
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (ImpDefRegs.count(Reg))
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return false;
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}
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++I;
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}
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I = MBB->begin();
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while (I != FirstTerm) {
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MachineInstr *ImpDefMI = &*I;
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++I;
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MBB->erase(ImpDefMI);
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}
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return true;
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}
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/// OptimizeFunction - Perhaps branch folding, tail merging and other
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/// OptimizeFunction - Perhaps branch folding, tail merging and other
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/// CFG optimizations on the given function. Block placement changes the layout
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/// CFG optimizations on the given function. Block placement changes the layout
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/// and may create new tail merging opportunities.
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/// and may create new tail merging opportunities.
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@ -228,7 +175,6 @@ bool BranchFolder::OptimizeFunction(MachineFunction &MF,
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SmallVector<MachineOperand, 4> Cond;
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SmallVector<MachineOperand, 4> Cond;
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if (!TII->analyzeBranch(MBB, TBB, FBB, Cond, true))
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if (!TII->analyzeBranch(MBB, TBB, FBB, Cond, true))
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MadeChange |= MBB.CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
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MadeChange |= MBB.CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
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MadeChange |= OptimizeImpDefsBlock(&MBB);
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}
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}
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// Recalculate funclet membership.
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// Recalculate funclet membership.
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@ -156,7 +156,6 @@ namespace llvm {
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bool OptimizeBranches(MachineFunction &MF);
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bool OptimizeBranches(MachineFunction &MF);
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bool OptimizeBlock(MachineBasicBlock *MBB);
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bool OptimizeBlock(MachineBasicBlock *MBB);
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void RemoveDeadBlock(MachineBasicBlock *MBB);
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void RemoveDeadBlock(MachineBasicBlock *MBB);
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bool OptimizeImpDefsBlock(MachineBasicBlock *MBB);
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bool HoistCommonCode(MachineFunction &MF);
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bool HoistCommonCode(MachineFunction &MF);
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bool HoistCommonCodeInSuccs(MachineBasicBlock *MBB);
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bool HoistCommonCodeInSuccs(MachineBasicBlock *MBB);
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@ -0,0 +1,29 @@
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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;
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; Check that the testcase compiles successfully. Expect that if-conversion
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; took place.
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; CHECK-LABEL: fred:
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; CHECK: if (!p0) r1 = memw(r0 + #0)
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target triple = "hexagon"
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define void @fred(i32 %p0) local_unnamed_addr align 2 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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%t0 = load i8*, i8** undef, align 4
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br label %b2
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b2: ; preds = %b1, %b0
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%t1 = phi i8* [ %t0, %b1 ], [ undef, %b0 ]
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%t2 = getelementptr inbounds i8, i8* %t1, i32 %p0
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tail call void @llvm.memmove.p0i8.p0i8.i32(i8* undef, i8* %t2, i32 undef, i32 1, i1 false) #1
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unreachable
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}
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declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind }
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@ -100,6 +100,7 @@ while.end: ; preds = %entry
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; CHECK-NEXT: in Loop: Header
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; CHECK-NEXT: in Loop: Header
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; CHECK-NEXT: incq
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; CHECK-NEXT: incq
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; CHECK-NEXT: %for.body3.us.i
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; CHECK-NEXT: %for.body3.us.i
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; CHECK-NEXT: Parent Loop
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; CHECK-NEXT: Inner Loop
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; CHECK-NEXT: Inner Loop
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; CHECK: testb
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; CHECK: testb
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; CHECK: je
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; CHECK: je
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