forked from OSchip/llvm-project
[ARM] Constant Mask VPT block tests. NFC
This commit is contained in:
David Green
parent
aaa925795f
commit
8254d70a38
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@ -147,6 +147,271 @@ entry:
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define arm_aapcs_vfpcc i32 @const_mask_1(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r1, #1
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #65534
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%8 = add i32 %6, %7
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%9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65534)
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)
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%11 = add i32 %8, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_not1(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_not1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r1, #1
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #65533
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%8 = add i32 %6, %7
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%9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65533)
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)
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%11 = add i32 %8, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_1234(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_1234:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%8 = add i32 %6, %7
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%9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)
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%11 = add i32 %8, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_abab(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_abab:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)
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%9 = add i32 %6, %8
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%11 = add i32 %9, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_abbreakab(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_abbreakab:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vadd.i32 q1, q0, r0
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; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)
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%9 = add i32 %6, %8
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%si = insertelement <4 x i32> undef, i32 %9, i32 0
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%s = shufflevector <4 x i32> %si, <4 x i32> undef, <4 x i32> zeroinitializer
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%nadd = add <4 x i32> %0, %s
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %nadd, i32 0, <4 x i1> %4)
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%11 = add i32 %9, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_break(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_break:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vadd.i32 q1, q0, r0
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%9 = add i32 %6, %8
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%si = insertelement <4 x i32> undef, i32 %9, i32 0
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%s = shufflevector <4 x i32> %si, <4 x i32> undef, <4 x i32> zeroinitializer
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%nadd = add <4 x i32> %0, %s
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %nadd, i32 0, <4 x i1> %7)
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%11 = add i32 %9, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_threepred(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_threepred:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #64300
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%9 = add i32 %6, %8
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%n7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64300)
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%n8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %n7)
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%n9 = add i32 %9, %n8
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)
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%11 = add i32 %n9, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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define arm_aapcs_vfpcc i32 @const_mask_threepredabab(<4 x i32> %0, <4 x i32> %1, i32 %2) {
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; CHECK-LABEL: const_mask_threepredabab:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: movw r1, #1234
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: movw r1, #64301
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; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vpt.s32 gt, q1, q0
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q1
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; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvat.s32 r0, q0
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: bx lr
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%4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1234)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
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%6 = add i32 %5, %2
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%7 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 64301)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %7)
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%9 = add i32 %6, %8
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%n7 = icmp slt <4 x i32> %0, %1
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%n8 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %n7)
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%n9 = add i32 %9, %n8
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%10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
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%11 = add i32 %n9, %10
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%12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %7)
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%13 = add i32 %11, %12
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ret i32 %13
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}
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declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
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