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[InstCombine] add tests for mul+lshr; NFC 

Baseline tests for D123453(issue #54824)
This commit is contained in:
chenglin.bi 2022-04-20 16:13:31 +08:00
parent 3d63d2111c
commit 8242fc7f8a
1 changed files with 70 additions and 0 deletions
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70
llvm/test/Transforms/InstCombine/shift-logic.ll
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@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare void @use(i64)
define i8 @shl_and(i8 %x, i8 %y) {
; CHECK-LABEL: @shl_and(
; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X:%.*]], 5
@ -254,3 +256,71 @@ define i32 @PR44028(i32 %x) {
%t27 = ashr exact i32 %t0, 16
ret i32 %t27
}
define i64 @lshr_mul(i64 %0) {
; CHECK-LABEL: @lshr_mul(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0:%.*]], 52
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i64 [[TMP2]], 2
; CHECK-NEXT: ret i64 [[TMP3]]
;
%2 = mul nuw i64 %0, 52
%3 = lshr i64 %2, 2
ret i64 %3
}
define i64 @lshr_mul_nuw_nsw(i64 %0) {
; CHECK-LABEL: @lshr_mul_nuw_nsw(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i64 [[TMP0:%.*]], 52
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i64 [[TMP2]], 2
; CHECK-NEXT: ret i64 [[TMP3]]
;
%2 = mul nuw nsw i64 %0, 52
%3 = lshr i64 %2, 2
ret i64 %3
}
define <4 x i32> @lshr_mul_vector(<4 x i32> %0) {
; CHECK-LABEL: @lshr_mul_vector(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP0:%.*]], <i32 52, i32 52, i32 52, i32 52>
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact <4 x i32> [[TMP2]], <i32 2, i32 2, i32 2, i32 2>
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
%2 = mul nuw <4 x i32> %0, <i32 52, i32 52, i32 52, i32 52>
%3 = lshr <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %3
}
define i64 @lshr_mul_negative_noexact(i64 %0) {
; CHECK-LABEL: @lshr_mul_negative_noexact(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0:%.*]], 53
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
; CHECK-NEXT: ret i64 [[TMP3]]
;
%2 = mul nuw i64 %0, 53
%3 = lshr i64 %2, 2
ret i64 %3
}
define i64 @lshr_mul_negative_oneuse(i64 %0) {
; CHECK-LABEL: @lshr_mul_negative_oneuse(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0:%.*]], 52
; CHECK-NEXT: call void @use(i64 [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i64 [[TMP2]], 2
; CHECK-NEXT: ret i64 [[TMP3]]
;
%2 = mul nuw i64 %0, 52
call void @use(i64 %2)
%3 = lshr i64 %2, 2
ret i64 %3
}
define i64 @lshr_mul_negative_nonuw(i64 %0) {
; CHECK-LABEL: @lshr_mul_negative_nonuw(
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP0:%.*]], 52
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i64 [[TMP2]], 2
; CHECK-NEXT: ret i64 [[TMP3]]
;
%2 = mul i64 %0, 52
%3 = lshr i64 %2, 2
ret i64 %3
}