forked from OSchip/llvm-project
[Hexagon] Lower vector predicate store
This patch lowers store of vector predicate of type v128i1.
This commit is contained in:
Ikhlas Ajbar
Krzysztof Parzyszek
parent
95291a0e34
commit
820df6e679
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@ -1681,6 +1681,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::STORE, VT, Custom);
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}
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setOperationAction(ISD::STORE, MVT::v128i1, Custom);
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for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
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MVT::v2i32}) {
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setCondCodeAction(ISD::SETNE, VT, Expand);
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@ -456,6 +456,8 @@ namespace HexagonISD {
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SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue HvxVecPredBitcastComputation(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
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@ -1437,17 +1437,12 @@ HexagonTargetLowering::LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const {
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return T7;
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}
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SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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SelectionDAG &DAG) const {
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auto *N = Op.getNode();
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EVT VT = N->getValueType(0);
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// This function does the computation needed to bitcast a vector of predicate
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// register to a vector of integers.
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SDValue
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HexagonTargetLowering::HvxVecPredBitcastComputation(SDValue Op,
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SelectionDAG &DAG) const {
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const SDLoc &dl(Op);
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SDValue Q0 = N->getOperand(0);
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EVT VTOp = Q0.getNode()->getValueType(0);
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if (!(VT == MVT::i64 || VT == MVT::i32) ||
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!(VTOp == MVT::v64i1 || VTOp == MVT::v32i1)) {
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return Op;
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}
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MVT VecTy;
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int Length;
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if (Subtarget.useHVX64BOps()) {
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@ -1463,7 +1458,7 @@ SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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SDValue InstrC8421 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C8421, DAG);
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// v0 = vand(q0,r0)
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SDValue Vand =
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getInstr(Hexagon::V6_vandqrt, dl, VecTy, {Q0, InstrC8421}, DAG);
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getInstr(Hexagon::V6_vandqrt, dl, VecTy, {Op, InstrC8421}, DAG);
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// Or the bytes in each word into a single byte: that will form packs
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// of 4 bits of the output.
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@ -1548,6 +1543,22 @@ SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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SDValue Vror2 = getInstr(Hexagon::V6_vror, dl, VecTy, {Vor3, InstrC4}, DAG);
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// v0 = vor(v0,v1)
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SDValue Vor4 = getInstr(Hexagon::V6_vor, dl, VecTy, {Vor3, Vror2}, DAG);
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return Vor4;
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}
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SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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SelectionDAG &DAG) const {
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auto *N = Op.getNode();
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EVT VT = N->getValueType(0);
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const SDLoc &dl(Op);
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SDValue Q0 = N->getOperand(0);
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EVT VTOp = Q0.getNode()->getValueType(0);
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if (!(VT == MVT::i64 || VT == MVT::i32) ||
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!(VTOp == MVT::v64i1 || VTOp == MVT::v32i1))
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return Op;
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SDValue Vor4 = HvxVecPredBitcastComputation(Q0, DAG);
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// The output is v.w[8]:v.w[0]
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// r3 = #0
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SDValue C0 = DAG.getTargetConstant(0, dl, MVT::i32);
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@ -1567,6 +1578,53 @@ SDValue HexagonTargetLowering::LowerHvxBitcast(SDValue Op,
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return Res;
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}
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SDValue HexagonTargetLowering::LowerHvxStore(SDValue Op,
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SelectionDAG &DAG) const {
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auto *N = Op.getNode();
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const SDLoc &dl(Op);
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SDValue Q0 = N->getOperand(1);
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EVT VTOp = Q0.getNode()->getValueType(0);
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if (Op.getOpcode() != ISD::STORE || VTOp != MVT::v128i1)
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return Op;
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SDValue Vor4 = HvxVecPredBitcastComputation(Q0, DAG);
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// The output is v.w[8]:v.w[0]
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// r3 = #0
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SDValue C0 = DAG.getTargetConstant(0, dl, MVT::i32);
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SDValue InstrC0 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C0, DAG);
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// r0 = vextract(v0,r3)
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SDValue Vextract0 =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC0}, DAG);
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// r3 = #32
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SDValue C32 = DAG.getTargetConstant(32, dl, MVT::i32);
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SDValue InstrC32 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C32, DAG);
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// r1 = vextract(v0,r3)
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SDValue Vextract1 =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC32}, DAG);
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SDValue Combine0 =
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getInstr(Hexagon::A2_combinew, dl, MVT::i64, {Vextract1, Vextract0}, DAG);
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// r3 = #64
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SDValue C64 = DAG.getTargetConstant(64, dl, MVT::i32);
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SDValue InstrC64 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C64, DAG);
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// r0 = vextract(v0,r3)
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SDValue Vextract2 =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC64}, DAG);
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// r3 = #96
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SDValue C96 = DAG.getTargetConstant(96, dl, MVT::i32);
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SDValue InstrC96 = getInstr(Hexagon::A2_tfrsi, dl, MVT::i32, C96, DAG);
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// r1 = vextract(v0,r3)
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SDValue Vextract3 =
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getInstr(Hexagon::V6_extractw, dl, MVT::i32, {Vor4, InstrC96}, DAG);
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SDValue Combine1 =
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getInstr(Hexagon::A2_combinew, dl, MVT::i64, {Vextract3, Vextract2}, DAG);
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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SDValue C8 = DAG.getTargetConstant(8, dl, MVT::i32);
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const SDValue Ops1[] = {ST->getBasePtr(), C8, Combine1, ST->getChain()};
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SDValue Store1 = getInstr(Hexagon::S2_storerd_io, dl, MVT::Other, Ops1, DAG);
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const SDValue Ops0[] = {ST->getBasePtr(), C0, Combine0, Store1};
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SDValue Store0 = getInstr(Hexagon::S2_storerd_io, dl, MVT::Other, Ops0, DAG);
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return Store0;
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}
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SDValue
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HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
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// Sign- and zero-extends are legal.
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@ -1740,6 +1798,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SETCC:
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case ISD::INTRINSIC_VOID: return Op;
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case ISD::INTRINSIC_WO_CHAIN: return LowerHvxIntrinsic(Op, DAG);
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case ISD::STORE: return LowerHvxStore(Op, DAG);
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// Unaligned loads will be handled by the default lowering.
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case ISD::LOAD: return SDValue();
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}
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@ -0,0 +1,47 @@
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; RUN: llc < %s | FileCheck %s
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; This test checks that store a vector predicate of type v128i1 is lowered
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; and two double stores are generated.
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; CHECK-DAG: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; CHECK-DAG: memd(r{{[0-9]+}}+#8) = r{{[0-9]+}}:{{[0-9]+}}
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target triple = "hexagon"
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define dso_local void @raac_UnpackADIFHeader() local_unnamed_addr #0 {
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entry:
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br i1 undef, label %cleanup, label %if.end
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if.end:
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%0 = load i8, i8* undef, align 1
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%conv13.i = zext i8 %0 to i32
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%trip.count.minus.1216 = add nsw i32 %conv13.i, -1
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%broadcast.splatinsert221 = insertelement <128 x i32> undef, i32 %trip.count.minus.1216, i32 0
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%broadcast.splat222 = shufflevector <128 x i32> %broadcast.splatinsert221, <128 x i32> undef, <128 x i32> zeroinitializer
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%1 = icmp ule <128 x i32> undef, %broadcast.splat222
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%wide.masked.load223 = call <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>* nonnull undef, i32 1, <128 x i1> %1, <128 x i8> undef)
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%2 = lshr <128 x i8> %wide.masked.load223, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
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%3 = and <128 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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%4 = zext <128 x i8> %3 to <128 x i32>
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%5 = add nsw <128 x i32> undef, %4
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%6 = select <128 x i1> %1, <128 x i32> %5, <128 x i32> undef
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%bin.rdx225 = add <128 x i32> %6, undef
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%bin.rdx227 = add <128 x i32> %bin.rdx225, undef
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%bin.rdx229 = add <128 x i32> %bin.rdx227, undef
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%bin.rdx231 = add <128 x i32> %bin.rdx229, undef
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%bin.rdx233 = add <128 x i32> %bin.rdx231, undef
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%bin.rdx235 = add <128 x i32> %bin.rdx233, undef
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%bin.rdx237 = add <128 x i32> %bin.rdx235, undef
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%7 = extractelement <128 x i32> %bin.rdx237, i32 0
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%nChans = getelementptr inbounds i8, i8* null, i32 2160
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%8 = bitcast i8* %nChans to i32*
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store i32 %7, i32* %8, align 4
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br label %cleanup
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cleanup:
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ret void
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}
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declare <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>*, i32 immarg, <128 x i1>, <128 x i8>)
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attributes #0 = { "target-features"="+hvx-length128b,+hvxv67,+v67,-long-calls" }
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