forked from OSchip/llvm-project
[Hexagon] Adding indexed store new-value variants.
llvm-svn: 225007
This commit is contained in:
Colin LeMahieu
parent
2bad4a7177
commit
820d5cb608
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@ -1559,7 +1559,7 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
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return Hexagon::STriw_nv_V4;
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case Hexagon::STriw_indexed_f:
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return Hexagon::STriw_indexed_nv_V4;
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return Hexagon::S2_storerinew_io;
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case Hexagon::STriw_shl_V4:
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return Hexagon::STriw_shl_nv_V4;
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@ -1097,62 +1097,117 @@ def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
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// NV/ST +
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//===----------------------------------------------------------------------===//
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let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
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class T_store_io_nv <string mnemonic, RegisterClass RC,
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Operand ImmOp, bits<2>MajOp>
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: NVInst_V4 <(outs),
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(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
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mnemonic#"($src1+#$src2) = $src3.new",
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[],"",ST_tc_st_SLOT0> {
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bits<5> src1;
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bits<13> src2; // Actual address offset
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bits<3> src3;
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bits<11> offsetBits; // Represents offset encoding
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let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
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!if (!eq(mnemonic, "memh"), 12,
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!if (!eq(mnemonic, "memw"), 13, 0)));
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let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
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!if (!eq(mnemonic, "memh"), 1,
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!if (!eq(mnemonic, "memw"), 2, 0)));
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let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
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!if (!eq(mnemonic, "memh"), src2{11-1},
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!if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
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let IClass = 0b1010;
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let Inst{27} = 0b0;
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let Inst{26-25} = offsetBits{10-9};
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let Inst{24-21} = 0b1101;
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let Inst{20-16} = src1;
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let Inst{13} = offsetBits{8};
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src3;
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let Inst{7-0} = offsetBits{7-0};
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}
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let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
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class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
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bits<2>MajOp, bit PredNot, bit isPredNew>
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: NVInst_V4 <(outs),
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(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
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!if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2+#$src3) = $src4.new",
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[],"",V2LDST_tc_st_SLOT0> {
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bits<2> src1;
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bits<5> src2;
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bits<9> src3;
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bits<3> src4;
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bits<6> offsetBits; // Represents offset encoding
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = PredNot;
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let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
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!if (!eq(mnemonic, "memh"), 7,
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!if (!eq(mnemonic, "memw"), 8, 0)));
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let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
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!if (!eq(mnemonic, "memh"), 1,
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!if (!eq(mnemonic, "memw"), 2, 0)));
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let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
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!if (!eq(mnemonic, "memh"), src3{6-1},
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!if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
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let IClass = 0b0100;
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let Inst{27} = 0b0;
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let Inst{26} = PredNot;
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let Inst{25} = isPredNew;
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let Inst{24-21} = 0b0101;
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let Inst{20-16} = src2;
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let Inst{13} = offsetBits{5};
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let Inst{12-11} = MajOp;
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let Inst{10-8} = src4;
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let Inst{7-3} = offsetBits{4-0};
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let Inst{2} = 0b0;
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let Inst{1-0} = src1;
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}
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// multiclass for new-value store instructions with base + immediate offset.
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//
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multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
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Operand predImmOp, bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2+#$src3) = $src4.new",
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[]>,
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Requires<[HasV4T]>;
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}
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multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
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bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
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}
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}
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let mayStore = 1, isNVStore = 1, hasSideEffects = 0, isExtendable = 1 in
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let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
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isExtendable = 1 in
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multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
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bits<5> PredImmBits> {
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Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
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let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1 in
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def NAME#_nv_V4 : NVInst_V4<(outs),
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(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
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mnemonic#"($src1+#$src2) = $src3.new",
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[]>,
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Requires<[HasV4T]>;
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let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
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isPredicated = 1 in {
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defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
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defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
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}
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def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
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// Predicated
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def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
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def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
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// Predicated new
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def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
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MajOp, 0, 1>;
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def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
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MajOp, 1, 1>;
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}
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}
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let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
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let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
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let accessSize = ByteAccess in
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defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 11, 6>, AddrModeRel;
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defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
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u6_0Ext, 0b00>, AddrModeRel;
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let accessSize = HalfWordAccess in
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defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 12, 7>, AddrModeRel;
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let accessSize = HalfWordAccess, opExtentAlign = 1 in
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defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
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u6_1Ext, 0b01>, AddrModeRel;
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let accessSize = WordAccess in
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defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 13, 8>, AddrModeRel;
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let accessSize = WordAccess, opExtentAlign = 2 in
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defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
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u6_2Ext, 0b10>, AddrModeRel;
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}
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// multiclass for new-value store instructions with base + immediate offset.
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@ -3,6 +3,9 @@
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0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(r17 + r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memb(r17+#21) = r2.new
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0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new
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@ -17,10 +20,27 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x40
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memb(r17+#21) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x44
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memb(r17+#21) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x42
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memb(r17+#21) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xc2 0xb1 0x46
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r2.new
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0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(r17 + r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memh(r17+#42) = r2.new
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0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new
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@ -35,10 +55,27 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x40
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memh(r17+#42) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x44
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memh(r17+#42) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x42
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memh(r17+#42) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xca 0xb1 0x46
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memh(r17+#42) = r2.new
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0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(r17 + r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1
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# CHECK: r31 = r31
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# CHECK-NEXT: memw(r17+#84) = r2.new
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0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new
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@ -53,3 +90,17 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x40
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# CHECK: r31 = r31
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# CHECK-NEXT: if (p3) memw(r17+#84) = r2.new
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0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x44
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# CHECK: r31 = r31
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# CHECK-NEXT: if (!p3) memw(r17+#84) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x42
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (p3.new) memw(r17+#84) = r2.new
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0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xd2 0xb1 0x46
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# CHECK: p3 = r5
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# CHECK-NEXT: r31 = r31
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# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r2.new
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