forked from OSchip/llvm-project
Rearrange code to reduce the nesting level. No functionality change.
llvm-svn: 59580
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a7c279ba40
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82016c243b
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@ -1754,44 +1754,44 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
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unsigned NumRes = TID.getNumDefs();
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unsigned NumOps = TID.getNumOperands() - NumRes;
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for (unsigned j = 0; j != NumOps; ++j) {
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if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
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SDNode *DU = SU->getNode()->getOperand(j).getNode();
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if (DU->getNodeId() == -1)
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if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
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continue;
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SDNode *DU = SU->getNode()->getOperand(j).getNode();
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if (DU->getNodeId() == -1)
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continue;
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const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
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if (!DUSU) continue;
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for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
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E = DUSU->Succs.end(); I != E; ++I) {
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if (I->isCtrl) continue;
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SUnit *SuccSU = I->Dep;
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if (SuccSU == SU)
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continue;
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const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
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if (!DUSU) continue;
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for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
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E = DUSU->Succs.end(); I != E; ++I) {
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if (I->isCtrl) continue;
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SUnit *SuccSU = I->Dep;
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if (SuccSU == SU)
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// Be conservative. Ignore if nodes aren't at roughly the same
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// depth and height.
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if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
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continue;
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if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
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continue;
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// Don't constrain nodes with physical register defs if the
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// predecessor can clobber them.
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if (SuccSU->hasPhysRegDefs) {
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if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
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continue;
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// Be conservative. Ignore if nodes aren't at roughly the same
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// depth and height.
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if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
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continue;
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if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
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continue;
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// Don't constrain nodes with physical register defs if the
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// predecessor can clobber them.
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if (SuccSU->hasPhysRegDefs) {
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if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
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continue;
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}
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// Don't constraint extract_subreg / insert_subreg these may be
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// coalesced away. We don't them close to their uses.
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unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
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if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
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SuccOpc == TargetInstrInfo::INSERT_SUBREG)
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continue;
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if ((!canClobber(SuccSU, DUSU) ||
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(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
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(!SU->isCommutable && SuccSU->isCommutable)) &&
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!scheduleDAG->IsReachable(SuccSU, SU)) {
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DOUT << "Adding an edge from SU # " << SU->NodeNum
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<< " to SU #" << SuccSU->NodeNum << "\n";
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scheduleDAG->AddPred(SU, SuccSU, true, true);
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}
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}
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// Don't constraint extract_subreg / insert_subreg these may be
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// coalesced away. We don't them close to their uses.
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unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
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if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
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SuccOpc == TargetInstrInfo::INSERT_SUBREG)
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continue;
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if ((!canClobber(SuccSU, DUSU) ||
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(hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
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(!SU->isCommutable && SuccSU->isCommutable)) &&
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!scheduleDAG->IsReachable(SuccSU, SU)) {
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DOUT << "Adding an edge from SU # " << SU->NodeNum
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<< " to SU #" << SuccSU->NodeNum << "\n";
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scheduleDAG->AddPred(SU, SuccSU, true, true);
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}
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}
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}
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