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[X86] Tighten up some inline assembly constraint handling. 

Don't allow vectors to split into GPRs for 'r' and other scalar
constraints. Prevents assertion in getCopyToPartsVector.

Makes PR50907 give a better error instead of crashing.
This commit is contained in:
Craig Topper 2021-06-26 22:48:56 -07:00
parent d8678246fc
commit 81f6d7c082
2 changed files with 24 additions and 7 deletions
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17
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -51790,7 +51790,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::GR16RegClass);
if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, &X86::GR32RegClass);
if (VT != MVT::f80)
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64RegClass);
break;
}
@ -51801,9 +51801,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
if (VT == MVT::i16)
return std::make_pair(0U, &X86::GR16_ABCDRegClass);
if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
return std::make_pair(0U, &X86::GR32_ABCDRegClass);
if (VT != MVT::f80)
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64_ABCDRegClass);
break;
case 'r': // GENERAL_REGS
@ -51812,9 +51813,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::GR8RegClass);
if (VT == MVT::i16)
return std::make_pair(0U, &X86::GR16RegClass);
if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
return std::make_pair(0U, &X86::GR32RegClass);
if (VT != MVT::f80)
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64RegClass);
break;
case 'R': // LEGACY_REGS
@ -51822,9 +51824,10 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::GR8_NOREXRegClass);
if (VT == MVT::i16)
return std::make_pair(0U, &X86::GR16_NOREXRegClass);
if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
return std::make_pair(0U, &X86::GR32_NOREXRegClass);
if (VT != MVT::f80)
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64_NOREXRegClass);
break;
case 'f': // FP Stack registers.

14
llvm/test/CodeGen/X86/pr50907.ll Normal file
View File

@ -0,0 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
; CHECK: error: couldn't allocate input reg for constraint 'r'
define i32 @f2() #0 {
entry:
%retval = alloca i32, align 4
%d = alloca <8 x i16>, align 16
%0 = load <8 x i16>, <8 x i16>* %d, align 16
call void asm sideeffect "", "r,~{dirflag},~{fpsr},~{flags}"(<8 x i16> %0)
%1 = load i32, i32* %retval, align 4
ret i32 %1
}