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[x86] enable machine combiner reassociations for scalar double-precision multiplies 

llvm-svn: 241873
This commit is contained in:
Sanjay Patel 2015-07-09 22:58:39 +00:00
parent bbdec4fc82
commit 81beefc541
2 changed files with 26 additions and 1 deletions
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4
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -6404,7 +6404,7 @@ static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
}
// TODO: There are many more machine instruction opcodes to match:
// 1. Other data types (double, integer, vectors)
// 1. Other data types (integer, vectors)
// 2. Other math / logic operations (and, or)
static bool isAssociativeAndCommutative(unsigned Opcode) {
switch (Opcode) {
@ -6412,7 +6412,9 @@ static bool isAssociativeAndCommutative(unsigned Opcode) {
case X86::ADDSSrr:
case X86::VADDSDrr:
case X86::VADDSSrr:
case X86::MULSDrr:
case X86::MULSSrr:
case X86::VMULSDrr:
case X86::VMULSSrr:
return true;
default:

23
llvm/test/CodeGen/X86/machine-combiner.ll
View File

@ -187,3 +187,26 @@ define double @reassociate_adds_double(double %x0, double %x1, double %x2, doubl
%t2 = fadd double %x3, %t1
ret double %t2
}
; Verify that SSE and AVX scalar double-precison multiplies are reassociated.
define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
; SSE-LABEL: reassociate_muls_double:
; SSE: # BB#0:
; SSE-NEXT: divsd %xmm1, %xmm0
; SSE-NEXT: mulsd %xmm3, %xmm2
; SSE-NEXT: mulsd %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: reassociate_muls_double:
; AVX: # BB#0:
; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmulsd %xmm3, %xmm2, %xmm1
; AVX-NEXT: vmulsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%t0 = fdiv double %x0, %x1
%t1 = fmul double %x2, %t0
%t2 = fmul double %x3, %t1
ret double %t2
}