forked from OSchip/llvm-project
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
llvm-svn: 171064
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@ -9173,7 +9173,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
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// If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
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// pcmpeqd + 2 shuffles + pand.
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// pcmpeqd + pshufd + pand.
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assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
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// First cast everything to the right type,
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@ -9184,11 +9184,9 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
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// Make sure the lower and upper halves are both all-ones.
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const int Mask1[] = { 0, 0, 2, 2 };
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SDValue S1 = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask1);
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const int Mask2[] = { 1, 1, 3, 3 };
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SDValue S2 = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask2);
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Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, S1, S2);
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const int Mask[] = { 1, 0, 3, 2 };
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SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
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Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
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if (Invert)
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Result = DAG.getNOT(dl, Result, MVT::v4i32);
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@ -45,8 +45,7 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
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define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK: test5:
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; CHECK: pcmpeqd
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; CHECK: pshufd $-11
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; CHECK: pshufd $-96
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; CHECK: pshufd $-79
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; CHECK: pand
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; CHECK: ret
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%C = icmp eq <2 x i64> %A, %B
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@ -57,8 +56,7 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
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define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK: test6:
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; CHECK: pcmpeqd
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; CHECK: pshufd $-11
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; CHECK: pshufd $-96
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; CHECK: pshufd $-79
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; CHECK: pand
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; CHECK: pcmpeqd
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; CHECK: pxor
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