forked from OSchip/llvm-project
Fix encoding of the immediate operands on post-indexed LDR and friends.
llvm-svn: 121354
This commit is contained in:
Owen Anderson
parent
a32986e899
commit
817b7cd7b8
|
|
@ -1310,74 +1310,61 @@ def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
|
|||
|
||||
// Indexed loads
|
||||
|
||||
class T2Iidxld<bit signed, bits<2> opcod, bit pre,
|
||||
dag oops, dag iops,
|
||||
AddrMode am, IndexMode im, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
: T2Iidxldst<signed, opcod, 1, pre, oops,
|
||||
iops, am,im,itin, opc, asm, cstr, pattern>;
|
||||
class T2Iidxst<bit signed, bits<2> opcod, bit pre,
|
||||
dag oops, dag iops,
|
||||
AddrMode am, IndexMode im, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
: T2Iidxldst<signed, opcod, 0, pre, oops,
|
||||
iops, am,im,itin, opc, asm, cstr, pattern>;
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
def t2LDR_PRE : T2Iidxld<0, 0b10, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins t2addrmode_imm8:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
|
||||
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
|
||||
[]>;
|
||||
|
||||
def t2LDR_POST : T2Iidxld<0, 0b10, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$offset),
|
||||
def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
|
||||
"ldr", "\t$Rt, [$Rn], $offset", "$base = $Rn",
|
||||
"ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
|
||||
[]>;
|
||||
|
||||
def t2LDRB_PRE : T2Iidxld<0, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins t2addrmode_imm8:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
|
||||
[]>;
|
||||
def t2LDRB_POST : T2Iidxld<0, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$offset),
|
||||
def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
"ldrb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
|
||||
"ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
|
||||
[]>;
|
||||
|
||||
def t2LDRH_PRE : T2Iidxld<0, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins t2addrmode_imm8:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
|
||||
[]>;
|
||||
def t2LDRH_POST : T2Iidxld<0, 0b01, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$offset),
|
||||
def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
"ldrh", "\t$Rt, [$Rn], $offset", "$base = $Rn",
|
||||
"ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
|
||||
[]>;
|
||||
|
||||
def t2LDRSB_PRE : T2Iidxld<1, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins t2addrmode_imm8:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
|
||||
[]>;
|
||||
def t2LDRSB_POST : T2Iidxld<1, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$offset),
|
||||
def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
"ldrsb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
|
||||
"ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
|
||||
[]>;
|
||||
|
||||
def t2LDRSH_PRE : T2Iidxld<1, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
|
||||
(ins t2addrmode_imm8:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
|
||||
[]>;
|
||||
def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$offset),
|
||||
def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
|
||||
(ins GPR:$base, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
"ldrsh", "\t$dst, [$Rn], $offset", "$base = $Rn",
|
||||
"ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
|
||||
[]>;
|
||||
} // mayLoad = 1, neverHasSideEffects = 1
|
||||
|
||||
|
|
@ -1424,42 +1411,42 @@ def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
|
|||
IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
|
||||
|
||||
// Indexed stores
|
||||
def t2STR_PRE : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
|
||||
def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
||||
"str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
|
||||
|
||||
def t2STR_POST : T2Iidxst<0, 0b10, 0, (outs GPR:$base_wb),
|
||||
def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
|
||||
"str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
|
||||
|
||||
def t2STRH_PRE : T2Iidxst<0, 0b01, 1, (outs GPR:$base_wb),
|
||||
def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
||||
"strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
|
||||
|
||||
def t2STRH_POST : T2Iidxst<0, 0b01, 0, (outs GPR:$base_wb),
|
||||
def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
|
||||
"strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
|
||||
|
||||
def t2STRB_PRE : T2Iidxst<0, 0b00, 1, (outs GPR:$base_wb),
|
||||
def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
|
||||
"strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
|
||||
|
||||
def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb),
|
||||
def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
|
||||
(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
|
||||
"strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
|
||||
|
|
|
|||
Loading…
Reference in New Issue