maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[CodeGen] Fixup assert fails caused by incorrect LoopInfo update 

Contributed-by: Star Tan <tanmx_star@yeah.net>
llvm-svn: 189764
This commit is contained in:
Tobias Grosser 2013-09-02 16:13:00 +00:00
parent 8f79ee99be
commit 815c635cec
3 changed files with 61 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
polly/lib/CodeGen/CodeGeneration.cpp
View File

@ -930,10 +930,8 @@ void ClastStmtCodeGen::codegen(const clast_guard *g) {
LoopInfo &LI = P->getAnalysis<LoopInfo>();
Loop *L = LI.getLoopFor(CondBB);
if (L) {
if (L)
L->addBasicBlockToLoop(ThenBB, LI.getBase());
L->addBasicBlockToLoop(MergeBB, LI.getBase());
}
codegen(g->then);

32
polly/test/Cloog/CodeGen/phi_guard.ll Normal file
View File

@ -0,0 +1,32 @@
; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-dir=%S -polly-codegen < %s
; This test case checks that Polly does not break for PHI guard statement.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i32 @phi_guard() {
entry:
%acc.reg2mem = alloca i32
br label %for.preheader
for.preheader: ; preds = %for.end, %entry
%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.end ]
store i32 0, i32* %acc.reg2mem
br label %for.inc
for.inc: ; preds = %for.inc, %for.preheader
%0 = phi i32 [ 0, %for.preheader ], [ %1, %for.inc ]
%1 = add nsw i32 %0, 1
store i32 %1, i32* %acc.reg2mem
%exitcond = icmp ne i32 %1, 20
br i1 %exitcond, label %for.inc, label %for.end
for.end: ; preds = %for.inc
%indvar.next = add i64 %indvar, 1
%exitcond4 = icmp ne i64 %indvar.next, 20
br i1 %exitcond4, label %for.preheader, label %for.end10
for.end10: ; preds = %for.end
%res = load i32* %acc.reg2mem, align 4
ret i32 %res
}

28
polly/test/Cloog/CodeGen/phi_guard___%for.preheader---%for.end10.jscop Normal file
View File

@ -0,0 +1,28 @@
{
"context" : "{ : }",
"name" : "for.preheader => for.end10",
"statements" : [
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_preheader[i0] -> MemRef_acc_reg2mem[0] }"
}
],
"domain" : "{ Stmt_for_preheader[i0] : i0 >= 0 and i0 <= 19 }",
"name" : "Stmt_for_preheader",
"schedule" : "{ Stmt_for_preheader[i0] -> [o0, o1, i0, 19i0, 0] : exists (e0 = [(o1)/32], e1 = [(o0)/32]: 32e0 = o1 and 32e1 = o0 and o0 <= i0 and o0 >= -31 + i0 and o1 <= 19i0 and o1 >= -31 + 19i0 and i0 >= 0 and i0 <= 19) }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_inc[i0, i1] -> MemRef_acc_reg2mem[0] }"
}
],
"domain" : "{ Stmt_for_inc[i0, i1] : i0 >= 0 and i0 <= 19 and i1 >= 0 and i1 <= 19 }",
"name" : "Stmt_for_inc",
"schedule" : "{ Stmt_for_inc[i0, i1] -> [o0, o1, i0, 19i0 + i1, 1] : exists (e0 = [(o1)/32], e1 = [(o0)/32]: 32e0 = o1 and 32e1 = o0 and o0 <= i0 and o0 >= -31 + i0 and o1 <= 19i0 + i1 and o1 >= -31 + 19i0 + i1 and i0 >= 0 and i0 <= 19 and i1 >= 0 and i1 <= 19) }"
}
]
}