forked from OSchip/llvm-project
parent
97879424fe
commit
812e1ea7cf
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@ -25,6 +25,7 @@
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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@ -47,11 +48,8 @@ namespace {
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bool runOnMachineFunction(MachineFunction &Fn);
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bool runOnMachineFunction(MachineFunction &Fn);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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}
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@ -516,6 +514,7 @@ void StrongPHIElimination::processPHIUnion(MachineInstr* Inst,
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/// of Static Single Assignment Form" by Briggs, et al.
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/// of Static Single Assignment Form" by Briggs, et al.
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void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
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void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
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std::set<unsigned>& pushed) {
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std::set<unsigned>& pushed) {
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// FIXME: This function needs to update LiveVariables
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std::map<unsigned, unsigned>& copy_set= Waiting[MBB];
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std::map<unsigned, unsigned>& copy_set= Waiting[MBB];
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std::map<unsigned, unsigned> worklist;
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std::map<unsigned, unsigned> worklist;
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@ -540,6 +539,8 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
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}
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}
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LiveVariables& LV = getAnalysis<LiveVariables>();
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LiveVariables& LV = getAnalysis<LiveVariables>();
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MachineFunction* MF = MBB->getParent();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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// Iterate over the worklist, inserting copies
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// Iterate over the worklist, inserting copies
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while (!worklist.empty() || !copy_set.empty()) {
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while (!worklist.empty() || !copy_set.empty()) {
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@ -547,13 +548,29 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
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std::pair<unsigned, unsigned> curr = *worklist.begin();
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std::pair<unsigned, unsigned> curr = *worklist.begin();
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worklist.erase(curr.first);
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worklist.erase(curr.first);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(curr.first);
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if (isLiveOut(LV.getVarInfo(curr.second), MBB)) {
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if (isLiveOut(LV.getVarInfo(curr.second), MBB)) {
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// Insert copy from curr.second to a temporary
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// Create a temporary
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unsigned t = MF->getRegInfo().createVirtualRegister(RC);
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// Insert copy from curr.second to a temporary at
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// the Phi defining curr.second
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LiveVariables::VarInfo VI = LV.getVarInfo(curr.second);
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MachineBasicBlock::iterator PI = VI.DefInst;
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TII->copyRegToReg(*VI.DefInst->getParent(), PI, t,
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curr.second, RC, RC);
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// Push temporary on Stacks
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// Push temporary on Stacks
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// Insert temporary in pushed
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Stacks[curr.second].push_back(t);
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// Insert curr.second in pushed
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pushed.insert(curr.second);
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}
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}
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// Insert copy from map[curr.first] to curr.second
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// Insert copy from map[curr.first] to curr.second
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TII->copyRegToReg(*MBB, MBB->end(), curr.second,
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map[curr.first], RC, RC);
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map[curr.first] = curr.second;
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map[curr.first] = curr.second;
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// If curr.first is a destination in copy_set...
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// If curr.first is a destination in copy_set...
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@ -577,8 +594,13 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
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std::pair<unsigned, unsigned> curr = *copy_set.begin();
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std::pair<unsigned, unsigned> curr = *copy_set.begin();
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copy_set.erase(curr.first);
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copy_set.erase(curr.first);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(curr.first);
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// Insert a copy from dest to a new temporary t at the end of b
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// Insert a copy from dest to a new temporary t at the end of b
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// map[curr.second] = t;
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unsigned t = MF->getRegInfo().createVirtualRegister(RC);
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TII->copyRegToReg(*MBB, MBB->end(), t,
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curr.second, RC, RC);
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map[curr.second] = t;
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worklist.insert(curr);
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worklist.insert(curr);
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}
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}
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@ -628,6 +650,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
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InsertCopies(Fn.begin());
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InsertCopies(Fn.begin());
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// FIXME: Perform renaming
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// FIXME: Perform renaming
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// FIXME: Remove Phi instrs
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return false;
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return false;
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}
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}
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