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[DAG] fold negation of sign-bit 

0 - X --> 0, if the sub is NUW
0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW
0 - X --> X, if X is 0 or the minimum signed value

This is the DAG equivalent of:
https://reviews.llvm.org/rL284649

plus the fold for the NUW case which already existed in InstSimplify.

Note that we miss a vector fold because of a deficiency in the DAG version of
computeKnownBits().

llvm-svn: 284844
This commit is contained in:
Sanjay Patel 2016-10-21 17:24:26 +00:00
parent 9fb40e3bbd
commit 81029f6a76
2 changed files with 31 additions and 24 deletions
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38
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1914,17 +1914,33 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
}
// Right-shifting everything out but the sign bit followed by negation is the
// same as flipping arithmetic/logical shift type without the negation:
// -(X >>u 31) -> (X >>s 31)
// -(X >>s 31) -> (X >>u 31)
if (isNullConstantOrNullSplatConstant(N0) &&
(N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL)) {
ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
if (ShiftAmt && ShiftAmt->getZExtValue() == VT.getScalarSizeInBits() - 1) {
auto NewOpc = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA;
if (!LegalOperations || TLI.isOperationLegal(NewOpc, VT))
return DAG.getNode(NewOpc, DL, VT, N1.getOperand(0), N1.getOperand(1));
if (isNullConstantOrNullSplatConstant(N0)) {
unsigned BitWidth = VT.getScalarSizeInBits();
// Right-shifting everything out but the sign bit followed by negation is
// the same as flipping arithmetic/logical shift type without the negation:
// -(X >>u 31) -> (X >>s 31)
// -(X >>s 31) -> (X >>u 31)
if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
if (ShiftAmt && ShiftAmt->getZExtValue() == BitWidth - 1) {
auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
}
}
// 0 - X --> 0 if the sub is NUW.
if (N->getFlags()->hasNoUnsignedWrap())
return N0;
if (DAG.MaskedValueIsZero(N1, ~APInt::getSignBit(BitWidth))) {
// N1 is either 0 or the minimum signed value. If the sub is NSW, then
// N1 must be 0 because negating the minimum signed value is undefined.
if (N->getFlags()->hasNoSignedWrap())
return N0;
// 0 - X --> X if X is 0 or the minimum signed value.
return N1;
}
}

17
llvm/test/CodeGen/X86/negate.ll
View File

@ -4,8 +4,7 @@
define i32 @negate_nuw(i32 %x) {
; CHECK-LABEL: negate_nuw:
; CHECK: # BB#0:
; CHECK-NEXT: negl %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
;
%neg = sub nuw i32 0, %x
@ -15,9 +14,7 @@ define i32 @negate_nuw(i32 %x) {
define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
; CHECK-LABEL: negate_nuw_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: psubd %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
;
%neg = sub nuw <4 x i32> zeroinitializer, %x
@ -27,9 +24,7 @@ define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
; CHECK-LABEL: negate_zero_or_minsigned_nsw:
; CHECK: # BB#0:
; CHECK-NEXT: andb $-128, %dil
; CHECK-NEXT: negb %dil
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
;
%signbit = and i8 %x, 128
@ -55,7 +50,6 @@ define i8 @negate_zero_or_minsigned(i8 %x) {
; CHECK-LABEL: negate_zero_or_minsigned:
; CHECK: # BB#0:
; CHECK-NEXT: shlb $7, %dil
; CHECK-NEXT: negb %dil
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
;
@ -67,10 +61,7 @@ define i8 @negate_zero_or_minsigned(i8 %x) {
define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
; CHECK-LABEL: negate_zero_or_minsigned_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: psubd %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
;
%signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>