forked from OSchip/llvm-project
[SelectionDAG] Add llvm.vector.{extract,insert} intrinsics
This commit adds two new intrinsics. - llvm.experimental.vector.insert: used to insert a vector into another vector starting at a given index. - llvm.experimental.vector.extract: used to extract a subvector from a larger vector starting from a given index. The codegen work for these intrinsics has already been completed; this commit is simply exposing the existing ISD nodes to LLVM IR. Reviewed By: cameron.mcinally Differential Revision: https://reviews.llvm.org/D91362
This commit is contained in:
Joe Ellis
parent
4167a0259e
commit
80c33de2d3
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@ -16095,6 +16095,81 @@ Arguments:
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""""""""""
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The argument to this intrinsic must be a vector of floating-point values.
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'``llvm.experimental.vector.insert``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic. You can use ``llvm.experimental.vector.insert``
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to insert a fixed-width vector into a scalable vector, but not the other way
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around.
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::
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declare <vscale x 4 x float> @llvm.experimental.vector.insert.v4f32(<vscale x 4 x float> %vec, <4 x float> %subvec, i64 %idx)
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declare <vscale x 2 x double> @llvm.experimental.vector.insert.v2f64(<vscale x 2 x double> %vec, <2 x double> %subvec, i64 %idx)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.insert.*``' intrinsics insert a vector into another vector
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starting from a given index. The return type matches the type of the vector we
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insert into. Conceptually, this can be used to build a scalable vector out of
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non-scalable vectors.
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Arguments:
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""""""""""
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The ``vec`` is the vector which ``subvec`` will be inserted into.
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The ``subvec`` is the vector that will be inserted.
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``idx`` represents the starting element number at which ``subvec`` will be
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inserted. ``idx`` must be a constant multiple of ``subvec``'s known minimum
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vector length. If ``subvec`` is a scalable vector, ``idx`` is first scaled by
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the runtime scaling factor of ``subvec``. The elements of ``vec`` starting at
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``idx`` are overwritten with ``subvec``. Elements ``idx`` through (``idx`` +
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num_elements(``subvec``) - 1) must be valid ``vec`` indices. If this condition
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cannot be determined statically but is false at runtime, then the result vector
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is undefined.
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'``llvm.experimental.vector.extract``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic. You can use
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``llvm.experimental.vector.extract`` to extract a fixed-width vector from a
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scalable vector, but not the other way around.
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::
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declare <4 x float> @llvm.experimental.vector.extract.v4f32(<vscale x 4 x float> %vec, i64 %idx)
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declare <2 x double> @llvm.experimental.vector.extract.v2f64(<vscale x 2 x double> %vec, i64 %idx)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.extract.*``' intrinsics extract a vector from
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within another vector starting from a given index. The return type must be
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explicitly specified. Conceptually, this can be used to decompose a scalable
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vector into non-scalable parts.
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Arguments:
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""""""""""
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The ``vec`` is the vector from which we will extract a subvector.
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The ``idx`` specifies the starting element number within ``vec`` from which a
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subvector is extracted. ``idx`` must be a constant multiple of the known-minimum
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vector length of the result type. If the result type is a scalable vector,
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``idx`` is first scaled by the result type's runtime scaling factor. Elements
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``idx`` through (``idx`` + num_elements(result_type) - 1) must be valid vector
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indices. If this condition cannot be determined statically but is false at
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runtime, then the result vector is undefined. The ``idx`` parameter must be a
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vector index constant type (for most targets this will be an integer pointer
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type).
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Matrix Intrinsics
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-----------------
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@ -1614,6 +1614,15 @@ def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
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//===---------- Intrinsics to query properties of scalable vectors --------===//
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def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
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//===---------- Intrinsics to perform subvector insertion/extraction ------===//
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def int_experimental_vector_insert : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty],
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[IntrNoMem, ImmArg<ArgIndex<2>>]>;
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def int_experimental_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, llvm_i64_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -6932,6 +6932,27 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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SetCC));
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return;
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}
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case Intrinsic::experimental_vector_insert: {
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auto DL = getCurSDLoc();
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SDValue Vec = getValue(I.getOperand(0));
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SDValue SubVec = getValue(I.getOperand(1));
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SDValue Index = getValue(I.getOperand(2));
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EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
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setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec,
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Index));
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return;
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}
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case Intrinsic::experimental_vector_extract: {
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auto DL = getCurSDLoc();
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SDValue Vec = getValue(I.getOperand(0));
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SDValue Index = getValue(I.getOperand(1));
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EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
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setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index));
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return;
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}
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}
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}
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@ -5138,6 +5138,26 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
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break;
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}
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case Intrinsic::experimental_vector_insert: {
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VectorType *VecTy = cast<VectorType>(Call.getArgOperand(0)->getType());
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VectorType *SubVecTy = cast<VectorType>(Call.getArgOperand(1)->getType());
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Assert(VecTy->getElementType() == SubVecTy->getElementType(),
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"experimental_vector_insert parameters must have the same element "
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"type.",
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&Call);
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break;
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}
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case Intrinsic::experimental_vector_extract: {
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VectorType *ResultTy = cast<VectorType>(Call.getType());
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VectorType *VecTy = cast<VectorType>(Call.getArgOperand(0)->getType());
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Assert(ResultTy->getElementType() == VecTy->getElementType(),
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"experimental_vector_extract result must have the same element "
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"type as the input vector.",
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&Call);
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break;
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}
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};
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}
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@ -1652,6 +1652,102 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
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}
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break;
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}
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case Intrinsic::experimental_vector_insert: {
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Value *Vec = II->getArgOperand(0);
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Value *SubVec = II->getArgOperand(1);
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Value *Idx = II->getArgOperand(2);
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auto *DstTy = dyn_cast<FixedVectorType>(II->getType());
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auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
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auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType());
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// Only canonicalize if the destination vector, Vec, and SubVec are all
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// fixed vectors.
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if (DstTy && VecTy && SubVecTy) {
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unsigned DstNumElts = DstTy->getNumElements();
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unsigned VecNumElts = VecTy->getNumElements();
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unsigned SubVecNumElts = SubVecTy->getNumElements();
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unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
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// The result of this call is undefined if IdxN is not a constant multiple
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// of the SubVec's minimum vector length OR the insertion overruns Vec.
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if (IdxN % SubVecNumElts != 0 || IdxN + SubVecNumElts > VecNumElts) {
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replaceInstUsesWith(CI, UndefValue::get(CI.getType()));
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return eraseInstFromFunction(CI);
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}
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// An insert that entirely overwrites Vec with SubVec is a nop.
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if (VecNumElts == SubVecNumElts) {
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replaceInstUsesWith(CI, SubVec);
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return eraseInstFromFunction(CI);
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}
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// Widen SubVec into a vector of the same width as Vec, since
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// shufflevector requires the two input vectors to be the same width.
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// Elements beyond the bounds of SubVec within the widened vector are
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// undefined.
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SmallVector<int, 8> WidenMask;
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unsigned i;
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for (i = 0; i != SubVecNumElts; ++i)
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WidenMask.push_back(i);
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for (; i != VecNumElts; ++i)
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WidenMask.push_back(UndefMaskElem);
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Value *WidenShuffle = Builder.CreateShuffleVector(
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SubVec, llvm::UndefValue::get(SubVecTy), WidenMask);
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SmallVector<int, 8> Mask;
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for (unsigned i = 0; i != IdxN; ++i)
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Mask.push_back(i);
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for (unsigned i = DstNumElts; i != DstNumElts + SubVecNumElts; ++i)
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Mask.push_back(i);
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for (unsigned i = IdxN + SubVecNumElts; i != DstNumElts; ++i)
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Mask.push_back(i);
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Value *Shuffle = Builder.CreateShuffleVector(Vec, WidenShuffle, Mask);
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replaceInstUsesWith(CI, Shuffle);
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return eraseInstFromFunction(CI);
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}
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break;
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}
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case Intrinsic::experimental_vector_extract: {
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Value *Vec = II->getArgOperand(0);
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Value *Idx = II->getArgOperand(1);
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auto *DstTy = dyn_cast<FixedVectorType>(II->getType());
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auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
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// Only canonicalize if the the destination vector and Vec are fixed
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// vectors.
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if (DstTy && VecTy) {
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unsigned DstNumElts = DstTy->getNumElements();
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unsigned VecNumElts = VecTy->getNumElements();
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unsigned IdxN = cast<ConstantInt>(Idx)->getZExtValue();
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// The result of this call is undefined if IdxN is not a constant multiple
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// of the result type's minimum vector length OR the extraction overruns
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// Vec.
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if (IdxN % DstNumElts != 0 || IdxN + DstNumElts > VecNumElts) {
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replaceInstUsesWith(CI, UndefValue::get(CI.getType()));
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return eraseInstFromFunction(CI);
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}
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// Extracting the entirety of Vec is a nop.
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if (VecNumElts == DstNumElts) {
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replaceInstUsesWith(CI, Vec);
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return eraseInstFromFunction(CI);
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}
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SmallVector<int, 8> Mask;
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for (unsigned i = 0; i != DstNumElts; ++i)
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Mask.push_back(IdxN + i);
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Value *Shuffle =
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Builder.CreateShuffleVector(Vec, UndefValue::get(VecTy), Mask);
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replaceInstUsesWith(CI, Shuffle);
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return eraseInstFromFunction(CI);
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}
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break;
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}
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default: {
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// Handle target specific intrinsics
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Optional<Instruction *> V = targetInstCombineIntrinsic(*II);
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@ -0,0 +1,138 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s --check-prefixes=CHECK
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s < %t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; Should codegen to a nop, since idx is zero.
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define <2 x i64> @extract_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind {
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; CHECK-LABEL: extract_v2i64_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 0)
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ret <2 x i64> %retval
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}
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; Goes through memory currently; idx != 0.
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define <2 x i64> @extract_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec) nounwind {
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; CHECK-LABEL: extract_v2i64_nxv2i64_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 1)
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ret <2 x i64> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <4 x i32> @extract_v4i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
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; CHECK-LABEL: extract_v4i32_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
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ret <4 x i32> %retval
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}
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; Goes through memory currently; idx != 0.
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define <4 x i32> @extract_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec) nounwind {
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; CHECK-LABEL: extract_v4i32_nxv4i32_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntw x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1w { z0.s }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #2
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 1)
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ret <4 x i32> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <8 x i16> @extract_v8i16_nxv8i16(<vscale x 8 x i16> %vec) nounwind {
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; CHECK-LABEL: extract_v8i16_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 0)
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ret <8 x i16> %retval
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}
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; Goes through memory currently; idx != 0.
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define <8 x i16> @extract_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec) nounwind {
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; CHECK-LABEL: extract_v8i16_nxv8i16_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cnth x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1h { z0.h }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #1
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 1)
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ret <8 x i16> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <16 x i8> @extract_v16i8_nxv16i8(<vscale x 16 x i8> %vec) nounwind {
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; CHECK-LABEL: extract_v16i8_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
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ret <16 x i8> %retval
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}
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; Goes through memory currently; idx != 0.
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define <16 x i8> @extract_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec) nounwind {
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; CHECK-LABEL: extract_v16i8_nxv16i8_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: st1b { z0.b }, p0, [sp]
|
||||
; CHECK-NEXT: csinc x8, x8, xzr, lo
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: ldr q0, [x9, x8]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 1)
|
||||
ret <16 x i8> %retval
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
|
||||
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
|
||||
declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64)
|
||||
declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s --check-prefixes=CHECK
|
||||
; RUN: FileCheck --check-prefix=WARN --allow-empty %s < %t
|
||||
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
|
||||
; WARN-NOT: warning
|
||||
|
||||
define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v2i64_nxv2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cntd x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #0 // =0
|
||||
; CHECK-NEXT: csel x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: lsl x8, x8, #3
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
|
||||
ret <vscale x 2 x i64> %retval
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v2i64_nxv2i64_idx1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cntd x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #1 // =1
|
||||
; CHECK-NEXT: csinc x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.d
|
||||
; CHECK-NEXT: lsl x8, x8, #3
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1d { z0.d }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 1)
|
||||
ret <vscale x 2 x i64> %retval
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v4i32_nxv4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cntw x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #0 // =0
|
||||
; CHECK-NEXT: csel x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.s
|
||||
; CHECK-NEXT: lsl x8, x8, #2
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1w { z0.s }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
|
||||
ret <vscale x 4 x i32> %retval
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v4i32_nxv4i32_idx1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cntw x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #1 // =1
|
||||
; CHECK-NEXT: csinc x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.s
|
||||
; CHECK-NEXT: lsl x8, x8, #2
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1w { z0.s }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 1)
|
||||
ret <vscale x 4 x i32> %retval
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v8i16_nxv8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cnth x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #0 // =0
|
||||
; CHECK-NEXT: csel x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.h
|
||||
; CHECK-NEXT: lsl x8, x8, #1
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1h { z0.h }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
|
||||
ret <vscale x 8 x i16> %retval
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v8i16_nxv8i16_idx1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: cnth x8
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #1 // =1
|
||||
; CHECK-NEXT: csinc x8, x8, xzr, lo
|
||||
; CHECK-NEXT: ptrue p0.h
|
||||
; CHECK-NEXT: lsl x8, x8, #1
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1h { z0.h }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 1)
|
||||
ret <vscale x 8 x i16> %retval
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v16i8_nxv16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: rdvl x8, #1
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #0 // =0
|
||||
; CHECK-NEXT: ptrue p0.b
|
||||
; CHECK-NEXT: csel x8, x8, xzr, lo
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1b { z0.b }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
|
||||
ret <vscale x 16 x i8> %retval
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
|
||||
; CHECK-LABEL: insert_v16i8_nxv16i8_idx1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: rdvl x8, #1
|
||||
; CHECK-NEXT: sub x8, x8, #1 // =1
|
||||
; CHECK-NEXT: cmp x8, #1 // =1
|
||||
; CHECK-NEXT: ptrue p0.b
|
||||
; CHECK-NEXT: csinc x8, x8, xzr, lo
|
||||
; CHECK-NEXT: mov x9, sp
|
||||
; CHECK-NEXT: st1b { z0.b }, p0, [sp]
|
||||
; CHECK-NEXT: str q1, [x9, x8]
|
||||
; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp]
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 1)
|
||||
ret <vscale x 16 x i8> %retval
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
|
||||
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
|
||||
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt < %s -instcombine -S | FileCheck %s
|
||||
|
||||
; llvm.experimental.vector.extract canonicalizes to shufflevector in the fixed case. In the
|
||||
; scalable case, we lower to the EXTRACT_SUBVECTOR ISD node.
|
||||
|
||||
declare <10 x i32> @llvm.experimental.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 %idx)
|
||||
declare <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 %idx)
|
||||
declare <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 %idx)
|
||||
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 %idx)
|
||||
declare <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 %idx)
|
||||
declare <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 %idx)
|
||||
|
||||
; ============================================================================ ;
|
||||
; Trivial cases
|
||||
; ============================================================================ ;
|
||||
|
||||
; Extracting the entirety of a vector is a nop.
|
||||
define <8 x i32> @trivial_nop(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @trivial_nop(
|
||||
; CHECK-NEXT: ret <8 x i32> [[VEC:%.*]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.extract.v8i32.v8i32(<8 x i32> %vec, i64 0)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Valid canonicalizations
|
||||
; ============================================================================ ;
|
||||
|
||||
define <2 x i32> @valid_extraction_a(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_a(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <2 x i32> <i32 0, i32 1>
|
||||
; CHECK-NEXT: ret <2 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 0)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
define <2 x i32> @valid_extraction_b(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_b(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
; CHECK-NEXT: ret <2 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 2)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
define <2 x i32> @valid_extraction_c(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_c(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <2 x i32> <i32 4, i32 5>
|
||||
; CHECK-NEXT: ret <2 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 4)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
define <2 x i32> @valid_extraction_d(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_d(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <2 x i32> <i32 6, i32 7>
|
||||
; CHECK-NEXT: ret <2 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v4i32(<8 x i32> %vec, i64 6)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @valid_extraction_e(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_e(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 0)
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <4 x i32> @valid_extraction_f(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_f(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 4)
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define <3 x i32> @valid_extraction_g(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_g(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
|
||||
; CHECK-NEXT: ret <3 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 0)
|
||||
ret <3 x i32> %1
|
||||
}
|
||||
|
||||
define <3 x i32> @valid_extraction_h(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @valid_extraction_h(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> undef, <3 x i32> <i32 3, i32 4, i32 5>
|
||||
; CHECK-NEXT: ret <3 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <3 x i32> @llvm.experimental.vector.extract.v3i32.v8i32(<8 x i32> %vec, i64 3)
|
||||
ret <3 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Invalid canonicalizations
|
||||
; ============================================================================ ;
|
||||
|
||||
; Idx must be the be a constant multiple of the destination vector's length,
|
||||
; otherwise the result is undefined.
|
||||
define <4 x i32> @idx_not_constant_multiple(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @idx_not_constant_multiple(
|
||||
; CHECK-NEXT: ret <4 x i32> undef
|
||||
;
|
||||
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.v8i32(<8 x i32> %vec, i64 1)
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
; If the extraction overruns the vector, the result is undefined.
|
||||
define <10 x i32> @extract_overrun(<8 x i32> %vec) {
|
||||
; CHECK-LABEL: @extract_overrun(
|
||||
; CHECK-NEXT: ret <10 x i32> undef
|
||||
;
|
||||
%1 = call <10 x i32> @llvm.experimental.vector.extract.v10i32.v8i32(<8 x i32> %vec, i64 0)
|
||||
ret <10 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Scalable cases
|
||||
; ============================================================================ ;
|
||||
|
||||
; Scalable extractions should not be canonicalized. This will be lowered to the
|
||||
; EXTRACT_SUBVECTOR ISD node later.
|
||||
define <4 x i32> @scalable_extract(<vscale x 4 x i32> %vec) {
|
||||
; CHECK-LABEL: @scalable_extract(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[VEC:%.*]], i64 0)
|
||||
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
|
||||
ret <4 x i32> %1
|
||||
}
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt < %s -instcombine -S | FileCheck %s
|
||||
|
||||
; llvm.experimental.vector.insert canonicalizes to shufflevector in the fixed case. In the
|
||||
; scalable case, we lower to the INSERT_SUBVECTOR ISD node.
|
||||
|
||||
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 %idx)
|
||||
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 %idx)
|
||||
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 %idx)
|
||||
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 %idx)
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 %idx)
|
||||
|
||||
; ============================================================================ ;
|
||||
; Trivial cases
|
||||
; ============================================================================ ;
|
||||
|
||||
; An insert that entirely overwrites an <n x ty> with another <n x ty> is a
|
||||
; nop.
|
||||
define <8 x i32> @trivial_nop(<8 x i32> %vec, <8 x i32> %subvec) {
|
||||
; CHECK-LABEL: @trivial_nop(
|
||||
; CHECK-NEXT: ret <8 x i32> [[SUBVEC:%.*]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 0)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Valid canonicalizations
|
||||
; ============================================================================ ;
|
||||
|
||||
define <8 x i32> @valid_insertion_a(<8 x i32> %vec, <2 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_a(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 0)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_b(<8 x i32> %vec, <2 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_b(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 2)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_c(<8 x i32> %vec, <2 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_c(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 4)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_d(<8 x i32> %vec, <2 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_d(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[SUBVEC:%.*]], <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v2i32(<8 x i32> %vec, <2 x i32> %subvec, i64 6)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_e(<8 x i32> %vec, <4 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_e(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 0)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_f(<8 x i32> %vec, <4 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_f(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SUBVEC:%.*]], <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 4)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_g(<8 x i32> %vec, <3 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_g(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[VEC:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 0)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
define <8 x i32> @valid_insertion_h(<8 x i32> %vec, <3 x i32> %subvec) {
|
||||
; CHECK-LABEL: @valid_insertion_h(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[SUBVEC:%.*]], <3 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[VEC:%.*]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 10, i32 6, i32 7>
|
||||
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v3i32(<8 x i32> %vec, <3 x i32> %subvec, i64 3)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Invalid canonicalizations
|
||||
; ============================================================================ ;
|
||||
|
||||
; Idx must be the be a constant multiple of the subvector's minimum vector
|
||||
; length, otherwise the result is undefined.
|
||||
define <8 x i32> @idx_not_constant_multiple(<8 x i32> %vec, <4 x i32> %subvec) {
|
||||
; CHECK-LABEL: @idx_not_constant_multiple(
|
||||
; CHECK-NEXT: ret <8 x i32> undef
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32> %vec, <4 x i32> %subvec, i64 2)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
; If the insertion overruns the vector, the result is undefined.
|
||||
define <8 x i32> @insert_overrun(<8 x i32> %vec, <8 x i32> %subvec) {
|
||||
; CHECK-LABEL: @insert_overrun(
|
||||
; CHECK-NEXT: ret <8 x i32> undef
|
||||
;
|
||||
%1 = call <8 x i32> @llvm.experimental.vector.insert.v8i32.v8i32(<8 x i32> %vec, <8 x i32> %subvec, i64 4)
|
||||
ret <8 x i32> %1
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Scalable cases
|
||||
; ============================================================================ ;
|
||||
|
||||
; Scalable insertions should not be canonicalized. This will be lowered to the
|
||||
; INSERT_SUBVECTOR ISD node later.
|
||||
define <vscale x 4 x i32> @scalable_insert(<vscale x 4 x i32> %vec, <4 x i32> %subvec) {
|
||||
; CHECK-LABEL: @scalable_insert(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> [[VEC:%.*]], <4 x i32> [[SUBVEC:%.*]], i64 0)
|
||||
; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
|
||||
ret <vscale x 4 x i32> %1
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s
|
||||
|
||||
; CHECK: experimental_vector_extract result must have the same element type as the input vector.
|
||||
define <16 x i16> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec) nounwind {
|
||||
%retval = call <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
|
||||
ret <16 x i16> %retval
|
||||
}
|
||||
|
||||
declare <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8>, i64)
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
; RUN: not opt -verify -S < %s 2>&1 >/dev/null | FileCheck %s
|
||||
|
||||
; CHECK: experimental_vector_insert parameters must have the same element type.
|
||||
define <vscale x 16 x i8> @invalid_mismatched_element_types(<vscale x 16 x i8> %vec, <4 x i16> %subvec) nounwind {
|
||||
%retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8> %vec, <4 x i16> %subvec, i64 0)
|
||||
ret <vscale x 16 x i8> %retval
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v4i16(<vscale x 16 x i8>, <4 x i16>, i64)
|
||||
Loading…
Reference in New Issue