forked from OSchip/llvm-project
Added Subtarget support into RegisterInfo
Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. llvm-svn: 53551
This commit is contained in:
Bruno Cardoso Lopes
parent
a696ca66e9
commit
80ab8f9649
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@ -15,6 +15,7 @@
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#define DEBUG_TYPE "mips-asm-printer"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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@ -44,21 +45,19 @@ STATISTIC(EmittedInsts, "Number of machine instrs printed");
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namespace {
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struct VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
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const MipsSubtarget *Subtarget;
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MipsAsmPrinter(std::ostream &O, MipsTargetMachine &TM,
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const TargetAsmInfo *T):
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AsmPrinter(O, TM, T) {}
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AsmPrinter(O, TM, T) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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}
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virtual const char *getPassName() const {
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return "Mips Assembly Printer";
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}
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enum SetDirectiveFlags {
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REORDER, // enables instruction reordering.
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NOREORDER, // disables instruction reordering.
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MACRO, // enables GAS macros.
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NOMACRO // disables GAS macros.
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};
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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@ -68,13 +67,13 @@ namespace {
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unsigned int getSavedRegsBitmask(bool isFloat, MachineFunction &MF);
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void printHex32(unsigned int Value);
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const char *emitCurrentABIString(void);
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void emitFunctionStart(MachineFunction &MF);
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void emitFunctionEnd(MachineFunction &MF);
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void emitFrameDirective(MachineFunction &MF);
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void emitMaskDirective(MachineFunction &MF);
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void emitFMaskDirective(MachineFunction &MF);
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void emitSetDirective(SetDirectiveFlags Flag);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -125,6 +124,10 @@ FunctionPass *llvm::createMipsCodePrinterPass(std::ostream &o,
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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/// Mask directive for GPR
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void MipsAsmPrinter::
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emitMaskDirective(MachineFunction &MF)
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@ -159,37 +162,6 @@ emitFMaskDirective(MachineFunction &MF)
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O << ",0" << "\n";
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}
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/// Frame Directive
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void MipsAsmPrinter::
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emitFrameDirective(MachineFunction &MF)
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{
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF.getFrameInfo()->getStackSize();
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O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).AsmName)
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<< "," << stackSize << ","
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<< "$" << LowercaseString(RI.get(returnReg).AsmName)
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<< "\n";
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}
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/// Emit Set directives.
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void MipsAsmPrinter::
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emitSetDirective(SetDirectiveFlags Flag)
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{
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O << "\t.set\t";
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switch(Flag) {
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case REORDER: O << "reorder" << "\n"; break;
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case NOREORDER: O << "noreorder" << "\n"; break;
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case MACRO: O << "macro" << "\n"; break;
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case NOMACRO: O << "nomacro" << "\n"; break;
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default: break;
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}
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}
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// Create a bitmask with all callee saved registers for CPU
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// or Floating Point registers. For CPU registers consider RA,
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// GP and FP for saving if necessary.
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@ -231,6 +203,44 @@ printHex32(unsigned int Value)
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O << std::dec;
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::
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emitFrameDirective(MachineFunction &MF)
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{
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF.getFrameInfo()->getStackSize();
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O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).AsmName)
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<< "," << stackSize << ","
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<< "$" << LowercaseString(RI.get(returnReg).AsmName)
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<< "\n";
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}
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/// Emit Set directives.
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const char * MipsAsmPrinter::
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emitCurrentABIString(void)
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{
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switch(Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O64: return "abiO64";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: break;
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}
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assert(0 && "Unknown Mips ABI");
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return NULL;
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}
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/// Emit the directives used by GAS on the start of functions
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void MipsAsmPrinter::
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emitFunctionStart(MachineFunction &MF)
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@ -244,18 +254,16 @@ emitFunctionStart(MachineFunction &MF)
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.ent\t" << CurrentFnName << "\n";
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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if ((TAI->hasDotTypeDotSizeDirective()) && Subtarget->isLinux())
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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O << CurrentFnName << ":\n";
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emitFrameDirective(MF);
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emitMaskDirective(MF);
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emitFMaskDirective(MF);
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if (TM.getRelocationModel() == Reloc::Static) {
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emitSetDirective(NOREORDER);
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emitSetDirective(NOMACRO);
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}
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O << "\n";
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}
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@ -263,12 +271,15 @@ emitFunctionStart(MachineFunction &MF)
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void MipsAsmPrinter::
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emitFunctionEnd(MachineFunction &MF)
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{
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if (TM.getRelocationModel() == Reloc::Static) {
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emitSetDirective(MACRO);
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emitSetDirective(REORDER);
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}
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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O << "\t.set\tmacro\n";
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O << "\t.set\treorder\n";
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O << "\t.end\t" << CurrentFnName << "\n";
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if (TAI->hasDotTypeDotSizeDirective() && !Subtarget->isLinux())
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O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << "\n";
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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@ -441,6 +452,18 @@ bool MipsAsmPrinter::
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doInitialization(Module &M)
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{
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Mang = new Mangler(M);
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// Tell the assembler which ABI we are using
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O << "\t.section .mdebug." << emitCurrentABIString() << "\n";
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// TODO: handle O64 ABI
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if (Subtarget->isABI_EABI())
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O << "\t.section .gcc_compiled_long" <<
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(Subtarget->isGP32bit() ? "32" : "64") << "\n";
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// return to previous section
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O << "\t.previous" << "\n";
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return false; // success
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}
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@ -548,8 +571,11 @@ doFinalization(Module &M)
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}
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O << "\t.align " << Align << "\n";
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O << "\t.type " << name << ",@object\n";
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O << "\t.size " << name << "," << Size << "\n";
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if (TAI->hasDotTypeDotSizeDirective()) {
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O << "\t.type " << name << ",@object\n";
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O << "\t.size " << name << "," << Size << "\n";
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}
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O << name << ":\n";
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EmitGlobalConstant(C);
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}
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@ -11,8 +11,9 @@
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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//#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "MipsGenInstrInfo.inc"
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@ -21,7 +22,7 @@ using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
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TM(tm), RI(*this) {}
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImmediate() && op.getImm() == 0;
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@ -31,7 +31,8 @@ def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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//def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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// Return
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@ -125,7 +126,7 @@ class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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@ -134,7 +135,7 @@ class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic 2 register operands
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@ -143,7 +144,7 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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@ -153,7 +154,7 @@ class MArithR<bits<6> func, string instr_asm> :
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func,
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, " $rs, $rt"),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[], IIImul>;
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// Logical
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@ -162,14 +163,14 @@ class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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@ -177,7 +178,7 @@ class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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@ -187,7 +188,7 @@ class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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@ -195,7 +196,7 @@ class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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// Load Upper Imediate
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@ -203,7 +204,7 @@ class LoadUpper<bits<6> op, string instr_asm>:
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FI< op,
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, " $dst, $imm"),
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!strconcat(instr_asm, "\t$dst, $imm"),
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[], IIAlu>;
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// Memory Load/Store
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@ -212,14 +213,14 @@ class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs),
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(ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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@ -228,7 +229,7 @@ class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, " $a, $b, $offset"),
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!strconcat(instr_asm, "\t$a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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@ -237,7 +238,7 @@ class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, " $src, $offset"),
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!strconcat(instr_asm, "\t$src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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@ -249,7 +250,7 @@ class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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@ -258,7 +259,7 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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@ -268,7 +269,7 @@ class JumpFJ<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, " $target"),
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!strconcat(instr_asm, "\t$target"),
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[(br bb:$target)], IIBranch>;
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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@ -277,7 +278,7 @@ class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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func,
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(outs),
|
||||
(ins CPURegs:$target),
|
||||
!strconcat(instr_asm, " $target"),
|
||||
!strconcat(instr_asm, "\t$target"),
|
||||
[(brind CPURegs:$target)], IIBranch>;
|
||||
|
||||
// Jump and Link (Call)
|
||||
|
|
@ -289,7 +290,7 @@ let isCall=1, hasDelaySlot=1,
|
|||
FJ< op,
|
||||
(outs),
|
||||
(ins calltarget:$target),
|
||||
!strconcat(instr_asm, " $target"),
|
||||
!strconcat(instr_asm, "\t$target"),
|
||||
[(MipsJmpLink imm:$target)], IIBranch>;
|
||||
|
||||
let rd=31 in
|
||||
|
|
@ -298,14 +299,14 @@ let isCall=1, hasDelaySlot=1,
|
|||
func,
|
||||
(outs),
|
||||
(ins CPURegs:$rs),
|
||||
!strconcat(instr_asm, " $rs"),
|
||||
!strconcat(instr_asm, "\t$rs"),
|
||||
[(MipsJmpLink CPURegs:$rs)], IIBranch>;
|
||||
|
||||
class BranchLink<string instr_asm>:
|
||||
FI< 0x1,
|
||||
(outs),
|
||||
(ins CPURegs:$rs, brtarget:$target),
|
||||
!strconcat(instr_asm, " $rs, $target"),
|
||||
!strconcat(instr_asm, "\t$rs, $target"),
|
||||
[], IIBranch>;
|
||||
}
|
||||
|
||||
|
|
@ -315,7 +316,7 @@ class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
|
|||
func,
|
||||
(outs),
|
||||
(ins CPURegs:$a, CPURegs:$b),
|
||||
!strconcat(instr_asm, " $a, $b"),
|
||||
!strconcat(instr_asm, "\t$a, $b"),
|
||||
[], itin>;
|
||||
|
||||
// Move from Hi/Lo
|
||||
|
|
@ -324,7 +325,7 @@ class MoveFromTo<bits<6> func, string instr_asm>:
|
|||
func,
|
||||
(outs CPURegs:$dst),
|
||||
(ins),
|
||||
!strconcat(instr_asm, " $dst"),
|
||||
!strconcat(instr_asm, "\t$dst"),
|
||||
[], IIHiLo>;
|
||||
|
||||
// Count Leading Ones/Zeros in Word
|
||||
|
|
@ -333,7 +334,7 @@ class CountLeading<bits<6> func, string instr_asm>:
|
|||
func,
|
||||
(outs CPURegs:$dst),
|
||||
(ins CPURegs:$src),
|
||||
!strconcat(instr_asm, " $dst, $src"),
|
||||
!strconcat(instr_asm, "\t$dst, $src"),
|
||||
[], IIAlu>;
|
||||
|
||||
class EffectiveAddress<string instr_asm> :
|
||||
|
|
@ -345,7 +346,7 @@ class EffectiveAddress<string instr_asm> :
|
|||
|
||||
class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
|
||||
FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
|
||||
!strconcat(instr_asm, " $dst, $src"),
|
||||
!strconcat(instr_asm, "\t$dst, $src"),
|
||||
[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
|
||||
|
||||
|
||||
|
|
@ -363,15 +364,19 @@ def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
|
|||
[(callseq_end imm:$amt1, imm:$amt2)]>;
|
||||
}
|
||||
|
||||
// Some assembly macros need to avoid pseudoinstructions and assembler
|
||||
// automatic reodering, we should reorder ourselves.
|
||||
def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
|
||||
def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
|
||||
def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
|
||||
def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
|
||||
|
||||
// When handling PIC code the assembler needs .cpload and .cprestore
|
||||
// directives. If the real instructions corresponding these directives
|
||||
// are used, we have the same behavior, but get also a bunch of warnings
|
||||
// from the assembler.
|
||||
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$reg),
|
||||
".set noreorder\n\t.cpload $reg\n\t.set reorder\n",
|
||||
[]>;
|
||||
def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc),
|
||||
".cprestore $loc\n", []>;
|
||||
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
|
||||
def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
|
||||
|
||||
// The supported Mips ISAs dont have any instruction close to the SELECT_CC
|
||||
// operation. The solution is to create a Mips pseudo SELECT_CC instruction
|
||||
|
|
@ -488,14 +493,14 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1,
|
|||
isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
|
||||
{
|
||||
def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
|
||||
"jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
|
||||
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
|
||||
}
|
||||
|
||||
// FrameIndexes are legalized when they are operands from load/store
|
||||
// instructions. The same not happens for stack address copies, so an
|
||||
// add op with mem ComplexPattern is used and the stack address copy
|
||||
// can be matched. It's similar to Sparc LEA_ADDRi
|
||||
def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
|
||||
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
|
||||
|
||||
// Count Leading
|
||||
// CLO/CLZ are part of the newer MIPS32(tm) instruction
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#define DEBUG_TYPE "mips-reg-info"
|
||||
|
||||
#include "Mips.h"
|
||||
#include "MipsSubtarget.h"
|
||||
#include "MipsRegisterInfo.h"
|
||||
#include "MipsMachineFunction.h"
|
||||
#include "llvm/Constants.h"
|
||||
|
|
@ -35,9 +36,10 @@
|
|||
|
||||
using namespace llvm;
|
||||
|
||||
MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
|
||||
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
||||
const TargetInstrInfo &tii)
|
||||
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
|
||||
TII(tii) {}
|
||||
Subtarget(ST), TII(tii) {}
|
||||
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
||||
|
|
@ -82,10 +84,10 @@ getRegisterNumbering(unsigned RegEnum)
|
|||
return 0; // Not reached
|
||||
}
|
||||
|
||||
unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; }
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Callee Saved Registers methods
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// Mips Callee Saved Registers
|
||||
|
|
@ -306,9 +308,12 @@ emitPrologue(MachineFunction &MF) const
|
|||
// Update frame info
|
||||
MFI->setStackSize(NumBytes);
|
||||
|
||||
// PIC speficic function prologue
|
||||
if (isPIC)
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER));
|
||||
|
||||
// TODO: check need from GP here.
|
||||
if (isPIC && Subtarget.isABI_O32())
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO));
|
||||
|
||||
// Adjust stack : addi sp, sp, (-imm)
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
|
||||
|
|
@ -334,9 +339,10 @@ emitPrologue(MachineFunction &MF) const
|
|||
}
|
||||
|
||||
// PIC speficic function prologue
|
||||
if ((isPIC) && (MFI->hasCalls()))
|
||||
if ((isPIC) && (MFI->hasCalls())) {
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
|
||||
.addImm(MipsFI->getGPStackOffset());
|
||||
}
|
||||
}
|
||||
|
||||
void MipsRegisterInfo::
|
||||
|
|
|
|||
|
|
@ -14,23 +14,28 @@
|
|||
#ifndef MIPSREGISTERINFO_H
|
||||
#define MIPSREGISTERINFO_H
|
||||
|
||||
#include "Mips.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "MipsGenRegisterInfo.h.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MipsSubtarget;
|
||||
class TargetInstrInfo;
|
||||
class Type;
|
||||
|
||||
struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
const MipsSubtarget &Subtarget;
|
||||
const TargetInstrInfo &TII;
|
||||
|
||||
MipsRegisterInfo(const TargetInstrInfo &tii);
|
||||
MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
|
||||
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||
|
||||
/// Get PIC indirect call register
|
||||
static unsigned getPICCallReg(void);
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
||||
|
||||
|
|
|
|||
|
|
@ -15,23 +15,34 @@
|
|||
#include "Mips.h"
|
||||
#include "MipsGenSubtarget.inc"
|
||||
#include "llvm/Module.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
using namespace llvm;
|
||||
|
||||
cl::opt<bool> NotABICall("disable-mips-abicall", cl::Hidden,
|
||||
cl::desc("Disable code for SVR4-style dynamic objects"));
|
||||
cl::opt<bool> AbsoluteCall("enable-mips-absolute-call", cl::Hidden,
|
||||
cl::desc("Enable absolute call within abicall"));
|
||||
|
||||
MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
|
||||
const std::string &FS, bool little) :
|
||||
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
|
||||
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false)
|
||||
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false),
|
||||
HasABICall(true), HasAbsoluteCall(false), IsLinux(true)
|
||||
{
|
||||
std::string CPU = "mips1";
|
||||
|
||||
// Parse features string.
|
||||
ParseSubtargetFeatures(FS, CPU);
|
||||
const std::string& TT = M.getTargetTriple();
|
||||
|
||||
// Is the target system Linux ?
|
||||
if (TT.find("linux") == std::string::npos)
|
||||
IsLinux = false;
|
||||
|
||||
// When only the target triple is specified and is
|
||||
// a allegrex target, set the features. We also match
|
||||
// big and little endian allegrex cores (dont really
|
||||
// know if a big one exists)
|
||||
const std::string& TT = M.getTargetTriple();
|
||||
if (TT.find("mipsallegrex") != std::string::npos) {
|
||||
MipsABI = EABI;
|
||||
IsSingleFloat = true;
|
||||
|
|
@ -39,4 +50,13 @@ MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
|
|||
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
|
||||
HasSEInReg = true;
|
||||
}
|
||||
|
||||
// Abicall is the default for O32 ABI and is ignored
|
||||
// for EABI.
|
||||
if (NotABICall || isABI_EABI())
|
||||
HasABICall = false;
|
||||
|
||||
// TODO: disable when handling 64 bit symbols in the future.
|
||||
if (HasABICall && AbsoluteCall)
|
||||
HasAbsoluteCall = true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,16 +24,17 @@ class Module;
|
|||
|
||||
class MipsSubtarget : public TargetSubtarget {
|
||||
|
||||
public:
|
||||
enum MipsABIEnum {
|
||||
O32, O64, N32, N64, EABI
|
||||
};
|
||||
|
||||
protected:
|
||||
|
||||
enum MipsArchEnum {
|
||||
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
|
||||
};
|
||||
|
||||
enum MipsABIEnum {
|
||||
O32, EABI
|
||||
};
|
||||
|
||||
// Mips architecture version
|
||||
MipsArchEnum MipsArchVersion;
|
||||
|
||||
|
|
@ -60,6 +61,16 @@ protected:
|
|||
// HasSEInReg - Target has SEB and SEH (signext in register) instructions.
|
||||
bool HasSEInReg;
|
||||
|
||||
// IsABICall - Enable SRV4 code for SVR4-style dynamic objects
|
||||
bool HasABICall;
|
||||
|
||||
// HasAbsoluteCall - Enable code that is not fully position-independent.
|
||||
// Only works with HasABICall enabled.
|
||||
bool HasAbsoluteCall;
|
||||
|
||||
// isLinux - Target system is Linux. Is false we consider ELFOS for now.
|
||||
bool IsLinux;
|
||||
|
||||
InstrItineraryData InstrItins;
|
||||
|
||||
public:
|
||||
|
|
@ -67,6 +78,7 @@ public:
|
|||
/// Only O32 and EABI supported right now.
|
||||
bool isABI_EABI() const { return MipsABI == EABI; }
|
||||
bool isABI_O32() const { return MipsABI == O32; }
|
||||
unsigned getTargetABI() const { return MipsABI; }
|
||||
|
||||
/// This constructor initializes the data members to match that
|
||||
/// of the specified module.
|
||||
|
|
@ -87,6 +99,9 @@ public:
|
|||
bool isNotSingleFloat() const { return !IsSingleFloat; };
|
||||
bool hasVFPU() const { return HasVFPU; };
|
||||
bool hasSEInReg() const { return HasSEInReg; };
|
||||
bool hasABICall() const { return HasABICall; };
|
||||
bool hasAbsoluteCall() const { return HasAbsoluteCall; };
|
||||
bool isLinux() const { return IsLinux; };
|
||||
|
||||
};
|
||||
} // End llvm namespace
|
||||
|
|
|
|||
|
|
@ -17,21 +17,23 @@
|
|||
using namespace llvm;
|
||||
|
||||
MipsTargetAsmInfo::MipsTargetAsmInfo(const MipsTargetMachine &TM) {
|
||||
AlignmentIsInBytes = false;
|
||||
Data16bitsDirective = "\t.half\t";
|
||||
Data32bitsDirective = "\t.word\t";
|
||||
PrivateGlobalPrefix = "$";
|
||||
JumpTableDataSection = "\t.rdata";
|
||||
CommentString = "#";
|
||||
ReadOnlySection = "\t.rdata";
|
||||
ZeroDirective = "\t.space\t";
|
||||
BSSSection = "\t.section\t.bss";
|
||||
LCOMMDirective = "\t.lcomm\t";
|
||||
|
||||
AlignmentIsInBytes = false;
|
||||
COMMDirectiveTakesAlignment = true;
|
||||
Data16bitsDirective = "\t.half\t";
|
||||
Data32bitsDirective = "\t.word\t";
|
||||
Data64bitsDirective = NULL;
|
||||
PrivateGlobalPrefix = "$";
|
||||
JumpTableDataSection = "\t.rdata";
|
||||
CommentString = "#";
|
||||
ReadOnlySection = "\t.rdata";
|
||||
ZeroDirective = "\t.space\t";
|
||||
BSSSection = "\t.section\t.bss";
|
||||
LCOMMDirective = "\t.lcomm\t";
|
||||
|
||||
if (TM.getRelocationModel() == Reloc::Static)
|
||||
JumpTableDirective = "\t.word\t";
|
||||
else
|
||||
JumpTableDirective = "\t.gpword\t";
|
||||
|
||||
COMMDirectiveTakesAlignment = true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,8 +44,12 @@ MipsTargetMachine(const Module &M, const std::string &FS, bool isLittle=false):
|
|||
FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
|
||||
TLInfo(*this)
|
||||
{
|
||||
if (getRelocationModel() != Reloc::Static)
|
||||
// Abicall enables PIC by default
|
||||
if (Subtarget.hasABICall() && (getRelocationModel() != Reloc::Static))
|
||||
setRelocationModel(Reloc::PIC_);
|
||||
|
||||
// TODO: create an option to enable long calls, like -mlong-calls,
|
||||
// that would be our CodeModel::Large. It must not work with Abicall.
|
||||
if (getCodeModel() == CodeModel::Default)
|
||||
setCodeModel(CodeModel::Small);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue