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Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified. 

llvm-svn: 199479
This commit is contained in:
Craig Topper 2014-01-17 08:16:57 +00:00
parent f124c6a5ef
commit 80ab268b06
3 changed files with 19 additions and 19 deletions
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16
llvm/lib/Target/X86/X86InstrArithmetic.td
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@ -1365,9 +1365,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
"adcx{l}\t{$src, $dst|$dst, $src}", "adcx{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8PD; [], IIC_BIN_NONMEM>, T8PD;
def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"adcx{q}\t{$src, $dst|$dst, $src}", "adcx{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8PD, REX_W, Requires<[In64BitMode]>; [], IIC_BIN_NONMEM>, T8PD, Requires<[In64BitMode]>;
} // SchedRW } // SchedRW
let mayLoad = 1, SchedRW = [WriteALULd] in { let mayLoad = 1, SchedRW = [WriteALULd] in {
@ -1375,9 +1375,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
"adcx{l}\t{$src, $dst|$dst, $src}", "adcx{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8PD; [], IIC_BIN_MEM>, T8PD;
def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"adcx{q}\t{$src, $dst|$dst, $src}", "adcx{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8PD, REX_W, Requires<[In64BitMode]>; [], IIC_BIN_MEM>, T8PD, Requires<[In64BitMode]>;
} }
} }
@ -1390,9 +1390,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
"adox{l}\t{$src, $dst|$dst, $src}", "adox{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8XS; [], IIC_BIN_NONMEM>, T8XS;
def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"adox{q}\t{$src, $dst|$dst, $src}", "adox{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>; [], IIC_BIN_NONMEM>, T8XS, Requires<[In64BitMode]>;
} // SchedRW } // SchedRW
let mayLoad = 1, SchedRW = [WriteALULd] in { let mayLoad = 1, SchedRW = [WriteALULd] in {
@ -1400,8 +1400,8 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
"adox{l}\t{$src, $dst|$dst, $src}", "adox{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8XS; [], IIC_BIN_MEM>, T8XS;
def ADOX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"adox{q}\t{$src, $dst|$dst, $src}", "adox{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>; [], IIC_BIN_MEM>, T8XS, Requires<[In64BitMode]>;
} }
} }

10
llvm/lib/Target/X86/X86InstrFPStack.td
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@ -621,13 +621,13 @@ def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE;
def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
"fxsave\t$dst", [], IIC_FXSAVE>, TB; "fxsave\t$dst", [], IIC_FXSAVE>, TB;
def FXSAVE64 : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
"fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB, REX_W, "fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
"fxrstor\t$src", [], IIC_FXRSTOR>, TB; "fxrstor\t$src", [], IIC_FXRSTOR>, TB;
def FXRSTOR64 : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
"fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB, REX_W, "fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} // SchedRW } // SchedRW

12
llvm/lib/Target/X86/X86InstrSystem.td
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@ -475,16 +475,16 @@ let Uses = [RDX, RAX, RCX] in
let Uses = [RDX, RAX] in { let Uses = [RDX, RAX] in {
def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
"xsave\t$dst", []>, TB; "xsave\t$dst", []>, TB;
def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins), def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
"xsave{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
"xrstor\t$dst", []>, TB; "xrstor\t$dst", []>, TB;
def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst), def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
"xrstor{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
"xsaveopt\t$dst", []>, TB; "xsaveopt\t$dst", []>, TB;
def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins), def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
"xsaveopt{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>; "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
} }
} // SchedRW } // SchedRW