forked from OSchip/llvm-project
Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified.
llvm-svn: 199479
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f124c6a5ef
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@ -1365,9 +1365,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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"adcx{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8PD;
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def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"adcx{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8PD, REX_W, Requires<[In64BitMode]>;
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[], IIC_BIN_NONMEM>, T8PD, Requires<[In64BitMode]>;
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} // SchedRW
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let mayLoad = 1, SchedRW = [WriteALULd] in {
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@ -1375,9 +1375,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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"adcx{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8PD;
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def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"adcx{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8PD, REX_W, Requires<[In64BitMode]>;
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[], IIC_BIN_MEM>, T8PD, Requires<[In64BitMode]>;
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}
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}
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@ -1390,9 +1390,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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"adox{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8XS;
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def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"adox{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>;
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[], IIC_BIN_NONMEM>, T8XS, Requires<[In64BitMode]>;
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} // SchedRW
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let mayLoad = 1, SchedRW = [WriteALULd] in {
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@ -1400,8 +1400,8 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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"adox{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8XS;
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def ADOX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"adox{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>;
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[], IIC_BIN_MEM>, T8XS, Requires<[In64BitMode]>;
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}
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}
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@ -621,13 +621,13 @@ def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE;
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def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
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"fxsave\t$dst", [], IIC_FXSAVE>, TB;
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def FXSAVE64 : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
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"fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB, REX_W,
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Requires<[In64BitMode]>;
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def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
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"fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB,
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Requires<[In64BitMode]>;
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def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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"fxrstor\t$src", [], IIC_FXRSTOR>, TB;
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def FXRSTOR64 : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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"fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB, REX_W,
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def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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"fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB,
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Requires<[In64BitMode]>;
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} // SchedRW
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@ -475,16 +475,16 @@ let Uses = [RDX, RAX, RCX] in
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let Uses = [RDX, RAX] in {
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def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
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"xsave\t$dst", []>, TB;
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def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
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"xsave{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
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def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
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"xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
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def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
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"xrstor\t$dst", []>, TB;
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def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
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"xrstor{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
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def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
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"xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
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def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveopt\t$dst", []>, TB;
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def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveopt{q|64}\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
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def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
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"xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
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}
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} // SchedRW
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