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[X86] Rename combineVSZext->combineExtendVectorInreg. NFC 

Now that we no longer have target specific vector extend nodes let's make the function name match the nodes we do use.

llvm-svn: 347268
This commit is contained in:
Craig Topper 2018-11-19 22:18:47 +00:00
parent cc870190d8
commit 808d0dd689
1 changed files with 4 additions and 4 deletions
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8
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -40494,9 +40494,9 @@ static SDValue combineSub(SDNode *N, SelectionDAG &DAG,
return combineAddOrSubToADCOrSBB(N, DAG);
}
static SDValue combineVSZext(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
static SDValue combineExtendVectorInreg(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
if (DCI.isBeforeLegalize())
return SDValue();
@ -40928,7 +40928,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
return combineVectorShiftImm(N, DAG, DCI, Subtarget);
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
return combineVSZext(N, DAG, DCI, Subtarget);
return combineExtendVectorInreg(N, DAG, DCI, Subtarget);
case X86ISD::PINSRB:
case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget);
case X86ISD::SHUFP: // Handle all target specific shuffles