forked from OSchip/llvm-project
[X86][SSE] Add SSE41 to variable permute tests
llvm-svn: 324017
This commit is contained in:
Simon Pilgrim
parent
11ee02fd39
commit
808a0e1589
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE,SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop | FileCheck %s --check-prefixes=AVX,AVXNOVLBW,XOP
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVXNOVLBW,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVXNOVLBW,AVX2
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@ -22,6 +23,18 @@ define <2 x i64> @var_shuffle_v2i64(<2 x i64> %v, <2 x i64> %indices) nounwind {
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; SSSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: var_shuffle_v2i64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq %xmm1, %rax
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; SSE41-NEXT: andl $1, %eax
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; SSE41-NEXT: pextrq $1, %xmm1, %rcx
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; SSE41-NEXT: andl $1, %ecx
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; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v2i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vpermilpd %xmm1, %xmm0, %xmm0
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@ -49,6 +62,13 @@ define <4 x i32> @var_shuffle_v4i32(<4 x i32> %v, <4 x i32> %indices) nounwind {
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; SSSE3-NEXT: pshufb %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: var_shuffle_v4i32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
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; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE41-NEXT: pshufb %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpermilps %xmm1, %xmm0, %xmm0
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@ -69,12 +89,12 @@ define <4 x i32> @var_shuffle_v4i32(<4 x i32> %v, <4 x i32> %indices) nounwind {
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}
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define <8 x i16> @var_shuffle_v8i16(<8 x i16> %v, <8 x i16> %indices) nounwind {
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; SSSE3-LABEL: var_shuffle_v8i16:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pmullw {{.*}}(%rip), %xmm1
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; SSSE3-NEXT: paddw {{.*}}(%rip), %xmm1
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; SSSE3-NEXT: pshufb %xmm1, %xmm0
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; SSSE3-NEXT: retq
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; SSE-LABEL: var_shuffle_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
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; SSE-NEXT: paddw {{.*}}(%rip), %xmm1
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; SSE-NEXT: pshufb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVXNOVLBW-LABEL: var_shuffle_v8i16:
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; AVXNOVLBW: # %bb.0:
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@ -115,10 +135,10 @@ define <8 x i16> @var_shuffle_v8i16(<8 x i16> %v, <8 x i16> %indices) nounwind {
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}
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define <16 x i8> @var_shuffle_v16i8(<16 x i8> %v, <16 x i8> %indices) nounwind {
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; SSSE3-LABEL: var_shuffle_v16i8:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb %xmm1, %xmm0
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; SSSE3-NEXT: retq
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; SSE-LABEL: var_shuffle_v16i8:
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; SSE: # %bb.0:
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; SSE-NEXT: pshufb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v16i8:
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; AVX: # %bb.0:
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@ -188,6 +208,17 @@ define <2 x double> @var_shuffle_v2f64(<2 x double> %v, <2 x i64> %indices) noun
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; SSSE3-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: var_shuffle_v2f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq %xmm1, %rax
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; SSE41-NEXT: andl $1, %eax
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; SSE41-NEXT: pextrq $1, %xmm1, %rcx
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; SSE41-NEXT: andl $1, %ecx
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; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE41-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vpermilpd %xmm1, %xmm0, %xmm0
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@ -215,6 +246,13 @@ define <4 x float> @var_shuffle_v4f32(<4 x float> %v, <4 x i32> %indices) nounwi
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; SSSE3-NEXT: pshufb %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: var_shuffle_v4f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
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; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE41-NEXT: pshufb %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpermilps %xmm1, %xmm0, %xmm0
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@ -235,10 +273,10 @@ define <4 x float> @var_shuffle_v4f32(<4 x float> %v, <4 x i32> %indices) nounwi
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}
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define <16 x i8> @var_shuffle_v16i8_from_v16i8_v32i8(<16 x i8> %v, <32 x i8> %indices) nounwind {
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; SSSE3-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufb %xmm1, %xmm0
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; SSSE3-NEXT: retq
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; SSE-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
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; SSE: # %bb.0:
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; SSE-NEXT: pshufb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v16i8_from_v16i8_v32i8:
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; AVX: # %bb.0:
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@ -435,6 +473,97 @@ define <16 x i8> @var_shuffle_v16i8_from_v32i8_v16i8(<32 x i8> %v, <16 x i8> %in
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; SSSE3-NEXT: popq %rbp
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pushq %rbp
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; SSE41-NEXT: movq %rsp, %rbp
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; SSE41-NEXT: andq $-32, %rsp
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; SSE41-NEXT: subq $544, %rsp # imm = 0x220
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; SSE41-NEXT: pextrb $0, %xmm2, %eax
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
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; SSE41-NEXT: movaps %xmm0, (%rsp)
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; SSE41-NEXT: movzbl 480(%rsp,%rax), %eax
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; SSE41-NEXT: movd %eax, %xmm0
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; SSE41-NEXT: pextrb $1, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $1, 448(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $2, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $2, 416(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $3, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $3, 384(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $4, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $4, 352(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $5, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $5, 320(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $6, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $6, 288(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $7, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $7, 256(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $8, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $8, 224(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $9, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $9, 192(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $10, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $10, 160(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $11, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $11, 128(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $12, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $12, 96(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $13, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $13, 64(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $14, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $14, 32(%rsp,%rax), %xmm0
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; SSE41-NEXT: pextrb $15, %xmm2, %eax
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; SSE41-NEXT: andl $31, %eax
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; SSE41-NEXT: pinsrb $15, (%rsp,%rax), %xmm0
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; SSE41-NEXT: movq %rbp, %rsp
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; SSE41-NEXT: popq %rbp
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: var_shuffle_v16i8_from_v32i8_v16i8:
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; AVX: # %bb.0:
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; AVX-NEXT: pushq %rbp
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