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[PowerPC] add more high latency opcodes for machine combiner pass 

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80097
This commit is contained in:
Chen Zheng 2020-05-21 02:04:10 -04:00
parent de71def3f5
commit 8086cdd1b0
2 changed files with 15 additions and 7 deletions
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10
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -235,10 +235,11 @@ void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI,
// This function does not list all associative and commutative operations, but // This function does not list all associative and commutative operations, but
// only those worth feeding through the machine combiner in an attempt to // only those worth feeding through the machine combiner in an attempt to
// reduce the critical path. Mostly, this means floating-point operations, // reduce the critical path. Mostly, this means floating-point operations,
// because they have high latencies (compared to other operations, such and // because they have high latencies(>=5) (compared to other operations, such as
// and/or, which are also associative and commutative, but have low latencies). // and/or, which are also associative and commutative, but have low latencies).
bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const { bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
// Floating point:
// FP Add: // FP Add:
case PPC::FADD: case PPC::FADD:
case PPC::FADDS: case PPC::FADDS:
@ -267,6 +268,13 @@ bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
case PPC::QVFMULSs: case PPC::QVFMULSs:
return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) && return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
Inst.getFlag(MachineInstr::MIFlag::FmNsz); Inst.getFlag(MachineInstr::MIFlag::FmNsz);
// Fixed point:
// Multiply:
case PPC::MULHD:
case PPC::MULLD:
case PPC::MULHW:
case PPC::MULLW:
return true;
default: default:
return false; return false;
} }

12
llvm/test/CodeGen/PowerPC/machine-combiner.ll
View File

@ -189,9 +189,9 @@ define double @reassociate_muls_double(double %x0, double %x1, double %x2, doubl
define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) { define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
; FIXPOINT-LABEL: reassociate_mullw: ; FIXPOINT-LABEL: reassociate_mullw:
; FIXPOINT: # %bb.0: ; FIXPOINT: # %bb.0:
; FIXPOINT: mullw 3, 3, 4 ; FIXPOINT: mullw [[REG0:[0-9]+]], 3, 4
; FIXPOINT: mullw 3, 3, 5 ; FIXPOINT: mullw [[REG1:[0-9]+]], 5, 6
; FIXPOINT: mullw 3, 3, 6 ; FIXPOINT: mullw 3, [[REG0]], [[REG1]]
; FIXPOINT-NEXT: blr ; FIXPOINT-NEXT: blr
%t0 = mul i32 %x0, %x1 %t0 = mul i32 %x0, %x1
@ -203,9 +203,9 @@ define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) { define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
; FIXPOINT-LABEL: reassociate_mulld: ; FIXPOINT-LABEL: reassociate_mulld:
; FIXPOINT: # %bb.0: ; FIXPOINT: # %bb.0:
; FIXPOINT: mulld 3, 3, 4 ; FIXPOINT: mulld [[REG0:[0-9]+]], 3, 4
; FIXPOINT: mulld 3, 3, 5 ; FIXPOINT: mulld [[REG1:[0-9]+]], 5, 6
; FIXPOINT: mulld 3, 3, 6 ; FIXPOINT: mulld 3, [[REG0]], [[REG1]]
; FIXPOINT-NEXT: blr ; FIXPOINT-NEXT: blr
%t0 = mul i64 %x0, %x1 %t0 = mul i64 %x0, %x1