forked from OSchip/llvm-project
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d0ed730f92
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@ -143,7 +143,7 @@ def PPCA2Itineraries : ProcessorItineraries<
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// A2 machine model for scheduling and other instruction cost heuristics.
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def PPCA2Model : SchedMachineModel {
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let IssueWidth = 1; // 2 micro-ops are dispatched per cycle.
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let IssueWidth = 1; // 1 instruction is dispatched per cycle.
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let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 6; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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