forked from OSchip/llvm-project
[SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts
This is mainly a move of simplifyShuffleOperands from DAGCombiner::visitVECTOR_SHUFFLE to create a more general purpose TargetLowering::SimplifyDemandedVectorElts implementation. Further features can be moved/added in future patches. Differential Revision: https://reviews.llvm.org/D42896 llvm-svn: 325232
This commit is contained in:
Simon Pilgrim
parent
9430c8cd1c
commit
80663ee986
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@ -2707,6 +2707,30 @@ public:
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bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
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DAGCombinerInfo &DCI) const;
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/// Look at Vector Op. At this point, we know that only the DemandedElts
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/// elements of the result of Op are ever used downstream. If we can use
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/// this information to simplify Op, create a new simplified DAG node and
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/// return true, storing the original and new nodes in TLO.
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/// Otherwise, analyze the expression and return a mask of KnownUndef and
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/// KnownZero elements for the expression (used to simplify the caller).
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/// The KnownUndef/Zero elements may only be accurate for those bits
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/// in the DemandedMask.
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/// \p AssumeSingleUse When this parameter is true, this function will
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/// attempt to simplify \p Op even if there are multiple uses.
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/// Callers are responsible for correctly updating the DAG based on the
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/// results of this function, because simply replacing replacing TLO.Old
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/// with TLO.New will be incorrect when this parameter is true and TLO.Old
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/// has multiple uses.
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bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
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APInt &KnownUndef, APInt &KnownZero,
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TargetLoweringOpt &TLO, unsigned Depth = 0,
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bool AssumeSingleUse = false) const;
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/// Helper wrapper around SimplifyDemandedVectorElts
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bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
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APInt &KnownUndef, APInt &KnownZero,
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DAGCombinerInfo &DCI) const;
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/// Determine which of the bits specified in Mask are known to be either zero
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/// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
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/// argument allows us to only collect the known bits that are shared by the
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@ -2735,6 +2759,15 @@ public:
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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/// Attempt to simplify any target nodes based on the demanded vector
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/// elements, returning true on success. Otherwise, analyze the expression and
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/// return a mask of KnownUndef and KnownZero elements for the expression
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/// (used to simplify the caller). The KnownUndef/Zero elements may only be
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/// accurate for those bits in the DemandedMask
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virtual bool SimplifyDemandedVectorEltsForTargetNode(
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SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
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APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
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struct DAGCombinerInfo {
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void *DC; // The DAG Combiner object.
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CombineLevel Level;
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@ -232,7 +232,17 @@ namespace {
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return SimplifyDemandedBits(Op, Demanded);
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}
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/// Check the specified vector node value to see if it can be simplified or
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/// if things it uses can be simplified as it only uses some of the
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/// elements. If so, return true.
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bool SimplifyDemandedVectorElts(SDValue Op) {
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unsigned NumElts = Op.getValueType().getVectorNumElements();
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APInt Demanded = APInt::getAllOnesValue(NumElts);
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return SimplifyDemandedVectorElts(Op, Demanded);
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}
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bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
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bool SimplifyDemandedVectorElts(SDValue Op, const APInt &Demanded);
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bool CombineToPreIndexedLoadStore(SDNode *N);
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bool CombineToPostIndexedLoadStore(SDNode *N);
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@ -1085,6 +1095,28 @@ bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
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return true;
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}
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/// Check the specified vector node value to see if it can be simplified or
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/// if things it uses can be simplified as it only uses some of the elements.
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/// If so, return true.
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bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
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const APInt &Demanded) {
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TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
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APInt KnownUndef, KnownZero;
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if (!TLI.SimplifyDemandedVectorElts(Op, Demanded, KnownUndef, KnownZero, TLO))
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return false;
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// Revisit the node.
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AddToWorklist(Op.getNode());
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// Replace the old value with the new one.
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++NodesCombined;
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DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);
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dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG); dbgs() << '\n');
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CommitTargetLoweringOpt(TLO);
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return true;
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}
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void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
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SDLoc DL(Load);
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EVT VT = Load->getValueType(0);
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@ -15558,92 +15590,6 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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return SDValue();
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}
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static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
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SDValue V, SelectionDAG &DAG) {
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SDLoc DL(V);
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EVT VT = V.getValueType();
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switch (V.getOpcode()) {
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default:
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return V;
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case ISD::CONCAT_VECTORS: {
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EVT OpVT = V->getOperand(0).getValueType();
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int OpSize = OpVT.getVectorNumElements();
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SmallBitVector OpUsedElements(OpSize, false);
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bool FoundSimplification = false;
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SmallVector<SDValue, 4> NewOps;
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NewOps.reserve(V->getNumOperands());
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for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
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SDValue Op = V->getOperand(i);
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bool OpUsed = false;
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for (int j = 0; j < OpSize; ++j)
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if (UsedElements[i * OpSize + j]) {
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OpUsedElements[j] = true;
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OpUsed = true;
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}
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NewOps.push_back(
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OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
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: DAG.getUNDEF(OpVT));
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FoundSimplification |= Op == NewOps.back();
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OpUsedElements.reset();
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}
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if (FoundSimplification)
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V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
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return V;
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}
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case ISD::INSERT_SUBVECTOR: {
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SDValue BaseV = V->getOperand(0);
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SDValue SubV = V->getOperand(1);
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auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
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if (!IdxN)
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return V;
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int SubSize = SubV.getValueType().getVectorNumElements();
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int Idx = IdxN->getZExtValue();
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bool SubVectorUsed = false;
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SmallBitVector SubUsedElements(SubSize, false);
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for (int i = 0; i < SubSize; ++i)
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if (UsedElements[i + Idx]) {
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SubVectorUsed = true;
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SubUsedElements[i] = true;
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UsedElements[i + Idx] = false;
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}
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// Now recurse on both the base and sub vectors.
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SDValue SimplifiedSubV =
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SubVectorUsed
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? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
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: DAG.getUNDEF(SubV.getValueType());
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SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
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if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
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V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
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SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
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return V;
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}
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}
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}
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static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
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SDValue N1, SelectionDAG &DAG) {
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EVT VT = SVN->getValueType(0);
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int NumElts = VT.getVectorNumElements();
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SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
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for (int M : SVN->getMask())
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if (M >= 0 && M < NumElts)
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N0UsedElements[M] = true;
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else if (M >= NumElts)
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N1UsedElements[M - NumElts] = true;
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SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
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SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
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if (S0 == N0 && S1 == N1)
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return SDValue();
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return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
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}
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static SDValue simplifyShuffleMask(ShuffleVectorSDNode *SVN, SDValue N0,
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SDValue N1, SelectionDAG &DAG) {
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auto isUndefElt = [](SDValue V, int Idx) {
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@ -16181,11 +16127,9 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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}
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// There are various patterns used to build up a vector from smaller vectors,
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// subvectors, or elements. Scan chains of these and replace unused insertions
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// or components with undef.
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if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
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return S;
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// Simplify source operands based on shuffle mask.
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if (SimplifyDemandedVectorElts(SDValue(N, 0)))
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return SDValue(N, 0);
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// Match shuffles that can be converted to any_vector_extend_in_reg.
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if (SDValue V = combineShuffleToVectorExtend(SVN, DAG, TLI, LegalOperations, LegalTypes))
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@ -1279,6 +1279,197 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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return false;
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}
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bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
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const APInt &DemandedElts,
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APInt &KnownUndef,
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APInt &KnownZero,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
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!DCI.isBeforeLegalizeOps());
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bool Simplified =
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SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
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if (Simplified)
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DCI.CommitTargetLoweringOpt(TLO);
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return Simplified;
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}
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bool TargetLowering::SimplifyDemandedVectorElts(
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SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef,
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APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
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bool AssumeSingleUse) const {
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EVT VT = Op.getValueType();
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APInt DemandedElts = DemandedEltMask;
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unsigned NumElts = DemandedElts.getBitWidth();
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assert(VT.isVector() && "Expected vector op");
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assert(VT.getVectorNumElements() == NumElts &&
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"Mask size mismatches value type element count!");
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KnownUndef = KnownZero = APInt::getNullValue(NumElts);
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// Undef operand.
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if (Op.isUndef()) {
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KnownUndef.setAllBits();
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return false;
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}
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// If Op has other users, assume that all elements are needed.
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if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
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DemandedElts.setAllBits();
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// Not demanding any elements from Op.
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if (DemandedElts == 0) {
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KnownUndef.setAllBits();
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return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
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}
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// Limit search depth.
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if (Depth >= 6)
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return false;
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SDLoc DL(Op);
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unsigned EltSizeInBits = VT.getScalarSizeInBits();
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switch (Op.getOpcode()) {
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case ISD::SCALAR_TO_VECTOR: {
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if (!DemandedElts[0]) {
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KnownUndef.setAllBits();
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return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
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}
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KnownUndef.setHighBits(NumElts - 1);
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break;
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}
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case ISD::BUILD_VECTOR: {
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// Check all elements and simplify any unused elements with UNDEF.
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if (!DemandedElts.isAllOnesValue()) {
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// Don't simplify BROADCASTS.
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if (llvm::any_of(Op->op_values(),
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[&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
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SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
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bool Updated = false;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (!DemandedElts[i] && !Ops[i].isUndef()) {
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Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
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KnownUndef.setBit(i);
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Updated = true;
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}
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}
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if (Updated)
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return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
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}
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}
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for (unsigned i = 0; i != NumElts; ++i) {
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SDValue SrcOp = Op.getOperand(i);
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if (SrcOp.isUndef()) {
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KnownUndef.setBit(i);
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} else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
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(isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
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KnownZero.setBit(i);
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}
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}
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break;
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}
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case ISD::CONCAT_VECTORS: {
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EVT SubVT = Op.getOperand(0).getValueType();
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unsigned NumSubVecs = Op.getNumOperands();
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unsigned NumSubElts = SubVT.getVectorNumElements();
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for (unsigned i = 0; i != NumSubVecs; ++i) {
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SDValue SubOp = Op.getOperand(i);
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APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
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APInt SubUndef, SubZero;
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if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
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Depth + 1))
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return true;
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KnownUndef.insertBits(SubUndef, i * NumSubElts);
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KnownZero.insertBits(SubZero, i * NumSubElts);
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}
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break;
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}
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case ISD::INSERT_SUBVECTOR: {
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if (!isa<ConstantSDNode>(Op.getOperand(2)))
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break;
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SDValue Base = Op.getOperand(0);
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SDValue Sub = Op.getOperand(1);
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EVT SubVT = Sub.getValueType();
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unsigned NumSubElts = SubVT.getVectorNumElements();
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APInt Idx = cast<ConstantSDNode>(Op.getOperand(2))->getAPIntValue();
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if (Idx.uge(NumElts - NumSubElts))
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break;
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unsigned SubIdx = Idx.getZExtValue();
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APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
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APInt SubUndef, SubZero;
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if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
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Depth + 1))
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return true;
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APInt BaseElts = DemandedElts;
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BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
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if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO,
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Depth + 1))
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return true;
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KnownUndef.insertBits(SubUndef, SubIdx);
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KnownZero.insertBits(SubZero, SubIdx);
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break;
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}
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case ISD::VECTOR_SHUFFLE: {
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ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
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// Collect demanded elements from shuffle operands..
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APInt DemandedLHS(NumElts, 0);
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APInt DemandedRHS(NumElts, 0);
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for (unsigned i = 0; i != NumElts; ++i) {
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int M = ShuffleMask[i];
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if (M < 0 || !DemandedElts[i])
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continue;
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assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
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if (M < (int)NumElts)
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DemandedLHS.setBit(M);
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else
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DemandedRHS.setBit(M - NumElts);
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}
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// See if we can simplify either shuffle operand.
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APInt UndefLHS, ZeroLHS;
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APInt UndefRHS, ZeroRHS;
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if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
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ZeroLHS, TLO, Depth + 1))
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return true;
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if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
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ZeroRHS, TLO, Depth + 1))
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return true;
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// Propagate undef/zero elements from LHS/RHS.
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for (unsigned i = 0; i != NumElts; ++i) {
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int M = ShuffleMask[i];
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if (M < 0) {
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KnownUndef.setBit(i);
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} else if (M < (int)NumElts) {
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if (UndefLHS[M])
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KnownUndef.setBit(i);
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if (ZeroLHS[M])
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KnownZero.setBit(i);
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} else {
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if (UndefRHS[M - NumElts])
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KnownUndef.setBit(i);
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if (ZeroRHS[M - NumElts])
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KnownZero.setBit(i);
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}
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}
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break;
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}
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default: {
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
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if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
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KnownZero, TLO, Depth))
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return true;
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break;
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}
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}
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assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero");
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return false;
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}
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/// Determine which of the bits specified in Mask are known to be either zero or
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/// one and return them in the Known.
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void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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@ -1323,6 +1514,18 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
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return 1;
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}
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bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
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SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
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TargetLoweringOpt &TLO, unsigned Depth) const {
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assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
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Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
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Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
|
||||
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
|
||||
"Should use SimplifyDemandedVectorElts if you don't know whether Op"
|
||||
" is a target node!");
|
||||
return false;
|
||||
}
|
||||
|
||||
// FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
|
||||
// work with truncating build vectors and vectors with elements of less than
|
||||
// 8 bits.
|
||||
|
|
|
|||
|
|
@ -50,40 +50,40 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x i8> %b) {
|
|||
;
|
||||
; MIPS32R5EB-LABEL: i8_2:
|
||||
; MIPS32R5EB: # %bb.0:
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, -16
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 16
|
||||
; MIPS32R5EB-NEXT: sw $5, 8($sp)
|
||||
; MIPS32R5EB-NEXT: sw $4, 12($sp)
|
||||
; MIPS32R5EB-NEXT: ldi.b $w0, 0
|
||||
; MIPS32R5EB-NEXT: lbu $1, 9($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 8($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w1, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 12($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[0], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 10($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 13($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[1], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 11($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 14($sp)
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 15($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[3], $1
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
|
||||
; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
|
||||
; MIPS32R5EB-NEXT: .cfi_offset 30, -4
|
||||
; MIPS32R5EB-NEXT: move $fp, $sp
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
|
||||
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
|
||||
; MIPS32R5EB-NEXT: and $sp, $sp, $1
|
||||
; MIPS32R5EB-NEXT: sw $5, 36($sp)
|
||||
; MIPS32R5EB-NEXT: sw $4, 40($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 37($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 20($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 36($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 16($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 40($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 41($sp)
|
||||
; MIPS32R5EB-NEXT: sw $2, 4($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 0($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w0, 16($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w0, $w0, $w0
|
||||
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 0($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w1, $w0
|
||||
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
|
||||
; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
|
||||
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[3]
|
||||
; MIPS32R5EB-NEXT: sb $2, 5($sp)
|
||||
; MIPS32R5EB-NEXT: sb $1, 4($sp)
|
||||
; MIPS32R5EB-NEXT: lhu $2, 4($sp)
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, 16
|
||||
; MIPS32R5EB-NEXT: sb $2, 33($sp)
|
||||
; MIPS32R5EB-NEXT: sb $1, 32($sp)
|
||||
; MIPS32R5EB-NEXT: lhu $2, 32($sp)
|
||||
; MIPS32R5EB-NEXT: move $sp, $fp
|
||||
; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
|
||||
; MIPS32R5EB-NEXT: jr $ra
|
||||
; MIPS32R5EB-NEXT: nop
|
||||
;
|
||||
|
|
@ -179,37 +179,37 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x i8> %b) {
|
|||
;
|
||||
; MIPS32R5EL-LABEL: i8_2:
|
||||
; MIPS32R5EL: # %bb.0:
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, -16
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 16
|
||||
; MIPS32R5EL-NEXT: sw $5, 8($sp)
|
||||
; MIPS32R5EL-NEXT: sw $4, 12($sp)
|
||||
; MIPS32R5EL-NEXT: ldi.b $w0, 0
|
||||
; MIPS32R5EL-NEXT: lbu $1, 9($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 12($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $3, 8($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w1, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[0], $3
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 10($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 11($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 13($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 14($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 15($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[3], $1
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
|
||||
; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
|
||||
; MIPS32R5EL-NEXT: .cfi_offset 30, -4
|
||||
; MIPS32R5EL-NEXT: move $fp, $sp
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
|
||||
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
|
||||
; MIPS32R5EL-NEXT: and $sp, $sp, $1
|
||||
; MIPS32R5EL-NEXT: sw $5, 36($sp)
|
||||
; MIPS32R5EL-NEXT: sw $4, 40($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 37($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 20($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 36($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 16($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 41($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 4($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 40($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 0($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w0, 16($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w0, $w0, $w0
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 0($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
|
||||
; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
|
||||
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
|
||||
; MIPS32R5EL-NEXT: sb $2, 5($sp)
|
||||
; MIPS32R5EL-NEXT: sb $1, 4($sp)
|
||||
; MIPS32R5EL-NEXT: lhu $2, 4($sp)
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, 16
|
||||
; MIPS32R5EL-NEXT: sb $2, 33($sp)
|
||||
; MIPS32R5EL-NEXT: sb $1, 32($sp)
|
||||
; MIPS32R5EL-NEXT: lhu $2, 32($sp)
|
||||
; MIPS32R5EL-NEXT: move $sp, $fp
|
||||
; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
|
||||
; MIPS32R5EL-NEXT: jr $ra
|
||||
; MIPS32R5EL-NEXT: nop
|
||||
;
|
||||
|
|
@ -364,102 +364,82 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x
|
|||
;
|
||||
; MIPS32R5EB-LABEL: i8x2_7:
|
||||
; MIPS32R5EB: # %bb.0: # %entry
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32R5EB-NEXT: sw $5, 16($sp)
|
||||
; MIPS32R5EB-NEXT: sw $4, 20($sp)
|
||||
; MIPS32R5EB-NEXT: ldi.b $w0, 0
|
||||
; MIPS32R5EB-NEXT: lbu $1, 17($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 16($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w1, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 18($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 21($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $3, 20($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[0], $3
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[1], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 19($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w1[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 22($sp)
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 23($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EB-NEXT: shf.w $w2, $w2, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w1, $w2, $w1
|
||||
; MIPS32R5EB-NEXT: sw $6, 12($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 13($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 12($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 14($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 15($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EB-NEXT: shf.w $w2, $w2, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EB-NEXT: sw $7, 8($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 9($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 8($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 10($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 11($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EB-NEXT: shf.w $w2, $w2, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EB-NEXT: lbu $1, 41($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 40($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 42($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 43($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EB-NEXT: shf.w $w2, $w2, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EB-NEXT: lbu $1, 45($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 44($sp)
|
||||
; MIPS32R5EB-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 46($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 47($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EB-NEXT: shf.w $w2, $w2, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EB-NEXT: lbu $1, 48($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[0], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 49($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[1], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 50($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[2], $1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 51($sp)
|
||||
; MIPS32R5EB-NEXT: insert.w $w0[3], $1
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, -144
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 144
|
||||
; MIPS32R5EB-NEXT: sw $fp, 140($sp) # 4-byte Folded Spill
|
||||
; MIPS32R5EB-NEXT: .cfi_offset 30, -4
|
||||
; MIPS32R5EB-NEXT: move $fp, $sp
|
||||
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
|
||||
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
|
||||
; MIPS32R5EB-NEXT: and $sp, $sp, $1
|
||||
; MIPS32R5EB-NEXT: sw $5, 132($sp)
|
||||
; MIPS32R5EB-NEXT: sw $4, 136($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 133($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 68($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 132($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 64($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 136($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $2, 137($sp)
|
||||
; MIPS32R5EB-NEXT: sw $2, 52($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 48($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w0, 64($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w0, $w0, $w0
|
||||
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 48($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w1, $w0
|
||||
; MIPS32R5EB-NEXT: sw $6, 128($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 129($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 84($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 128($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 80($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 80($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: sw $7, 124($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 125($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 100($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 124($sp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 96($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 96($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 161($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 4($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 160($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 0($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 0($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 165($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 20($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 164($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 16($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 16($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: lbu $1, 169($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 36($sp)
|
||||
; MIPS32R5EB-NEXT: lbu $1, 168($fp)
|
||||
; MIPS32R5EB-NEXT: sw $1, 32($sp)
|
||||
; MIPS32R5EB-NEXT: ld.w $w1, 32($sp)
|
||||
; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
|
||||
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
|
||||
; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
|
||||
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[3]
|
||||
; MIPS32R5EB-NEXT: sb $2, 5($sp)
|
||||
; MIPS32R5EB-NEXT: sb $1, 4($sp)
|
||||
; MIPS32R5EB-NEXT: lhu $2, 4($sp)
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32R5EB-NEXT: sb $2, 121($sp)
|
||||
; MIPS32R5EB-NEXT: sb $1, 120($sp)
|
||||
; MIPS32R5EB-NEXT: lhu $2, 120($sp)
|
||||
; MIPS32R5EB-NEXT: move $sp, $fp
|
||||
; MIPS32R5EB-NEXT: lw $fp, 140($sp) # 4-byte Folded Reload
|
||||
; MIPS32R5EB-NEXT: addiu $sp, $sp, 144
|
||||
; MIPS32R5EB-NEXT: jr $ra
|
||||
; MIPS32R5EB-NEXT: nop
|
||||
;
|
||||
|
|
@ -720,94 +700,74 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x
|
|||
;
|
||||
; MIPS32R5EL-LABEL: i8x2_7:
|
||||
; MIPS32R5EL: # %bb.0: # %entry
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32R5EL-NEXT: sw $5, 16($sp)
|
||||
; MIPS32R5EL-NEXT: ldi.b $w0, 0
|
||||
; MIPS32R5EL-NEXT: sw $4, 20($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 17($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 16($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w1, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 18($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 19($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w1[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 21($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 20($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 22($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 23($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EL-NEXT: addv.d $w1, $w2, $w1
|
||||
; MIPS32R5EL-NEXT: sw $6, 12($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 13($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 12($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 14($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 15($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EL-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EL-NEXT: sw $7, 8($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 9($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 8($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 10($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 11($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EL-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EL-NEXT: lbu $1, 41($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 40($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 42($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 43($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EL-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EL-NEXT: lbu $1, 45($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $2, 44($sp)
|
||||
; MIPS32R5EL-NEXT: move.v $w2, $w0
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[0], $2
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 46($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 47($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w2[3], $1
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w2, $w2, $w2
|
||||
; MIPS32R5EL-NEXT: addv.d $w1, $w1, $w2
|
||||
; MIPS32R5EL-NEXT: lbu $1, 48($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[0], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 49($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[1], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 50($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[2], $1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 51($sp)
|
||||
; MIPS32R5EL-NEXT: insert.w $w0[3], $1
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, -144
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 144
|
||||
; MIPS32R5EL-NEXT: sw $fp, 140($sp) # 4-byte Folded Spill
|
||||
; MIPS32R5EL-NEXT: .cfi_offset 30, -4
|
||||
; MIPS32R5EL-NEXT: move $fp, $sp
|
||||
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
|
||||
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
|
||||
; MIPS32R5EL-NEXT: and $sp, $sp, $1
|
||||
; MIPS32R5EL-NEXT: sw $5, 132($sp)
|
||||
; MIPS32R5EL-NEXT: sw $4, 136($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 133($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 68($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 132($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 64($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 137($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 52($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 136($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 48($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w0, 64($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w0, $w0, $w0
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 48($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
|
||||
; MIPS32R5EL-NEXT: sw $6, 128($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 129($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 84($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 128($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 80($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 80($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: sw $7, 124($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 125($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 100($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 124($sp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 96($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 96($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 161($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 4($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 160($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 0($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 0($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 165($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 20($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 164($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 16($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 16($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: lbu $1, 169($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 36($sp)
|
||||
; MIPS32R5EL-NEXT: lbu $1, 168($fp)
|
||||
; MIPS32R5EL-NEXT: sw $1, 32($sp)
|
||||
; MIPS32R5EL-NEXT: ld.w $w1, 32($sp)
|
||||
; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
|
||||
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
|
||||
; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
|
||||
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
|
||||
; MIPS32R5EL-NEXT: sb $2, 5($sp)
|
||||
; MIPS32R5EL-NEXT: sb $1, 4($sp)
|
||||
; MIPS32R5EL-NEXT: lhu $2, 4($sp)
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32R5EL-NEXT: sb $2, 121($sp)
|
||||
; MIPS32R5EL-NEXT: sb $1, 120($sp)
|
||||
; MIPS32R5EL-NEXT: lhu $2, 120($sp)
|
||||
; MIPS32R5EL-NEXT: move $sp, $fp
|
||||
; MIPS32R5EL-NEXT: lw $fp, 140($sp) # 4-byte Folded Reload
|
||||
; MIPS32R5EL-NEXT: addiu $sp, $sp, 144
|
||||
; MIPS32R5EL-NEXT: jr $ra
|
||||
; MIPS32R5EL-NEXT: nop
|
||||
;
|
||||
|
|
|
|||
|
|
@ -239,10 +239,7 @@ define <4 x i32> @combine_vec_ashr_trunc_lshr(<4 x i64> %x) {
|
|||
define <4 x i32> @combine_vec_ashr_trunc_ashr(<4 x i64> %x) {
|
||||
; SSE-LABEL: combine_vec_ashr_trunc_ashr:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
|
||||
; SSE-NEXT: psrad $31, %xmm1
|
||||
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
|
||||
; SSE-NEXT: movaps %xmm0, %xmm2
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: psrad $2, %xmm1
|
||||
|
|
|
|||
|
|
@ -20,10 +20,7 @@ define <4 x i64> @autogen_SD88863() {
|
|||
;
|
||||
; X64-LABEL: autogen_SD88863:
|
||||
; X64: # %bb.0: # %BB
|
||||
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5],ymm1[6,7]
|
||||
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
|
||||
; X64-NEXT: movb $1, %al
|
||||
; X64-NEXT: .p2align 4, 0x90
|
||||
; X64-NEXT: .LBB0_1: # %CF
|
||||
|
|
@ -31,6 +28,9 @@ define <4 x i64> @autogen_SD88863() {
|
|||
; X64-NEXT: testb %al, %al
|
||||
; X64-NEXT: jne .LBB0_1
|
||||
; X64-NEXT: # %bb.2: # %CF240
|
||||
; X64-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
|
||||
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
|
||||
; X64-NEXT: retq
|
||||
BB:
|
||||
%I26 = insertelement <4 x i64> undef, i64 undef, i32 2
|
||||
|
|
|
|||
|
|
@ -917,8 +917,6 @@ define <4 x float> @test_mm_loadh_pi(<4 x float> %a0, x86_mmx* %a1) {
|
|||
; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||
; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; X64-NEXT: xorps %xmm2, %xmm2
|
||||
; X64-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; X64-NEXT: retq
|
||||
%ptr = bitcast x86_mmx* %a1 to <2 x float>*
|
||||
|
|
@ -948,8 +946,6 @@ define <4 x float> @test_mm_loadl_pi(<4 x float> %a0, x86_mmx* %a1) {
|
|||
; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||
; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; X64-NEXT: xorps %xmm2, %xmm2
|
||||
; X64-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
|
||||
; X64-NEXT: movaps %xmm1, %xmm0
|
||||
; X64-NEXT: retq
|
||||
|
|
|
|||
|
|
@ -379,16 +379,12 @@ entry:
|
|||
define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone {
|
||||
; X86-LABEL: t16:
|
||||
; X86: # %bb.0: # %entry
|
||||
; X86-NEXT: movdqa {{.*#+}} xmm1 = [0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0]
|
||||
; X86-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
||||
; X86-NEXT: movdqa %xmm1, %xmm0
|
||||
; X86-NEXT: pslld $16, %xmm0
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: t16:
|
||||
; X64: # %bb.0: # %entry
|
||||
; X64-NEXT: movdqa {{.*#+}} xmm1 = [0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0]
|
||||
; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
||||
; X64-NEXT: movdqa %xmm1, %xmm0
|
||||
; X64-NEXT: pslld $16, %xmm0
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
|
||||
|
|
|
|||
|
|
@ -511,10 +511,9 @@ define <8 x float> @expand14(<4 x float> %a) {
|
|||
;
|
||||
; KNL64-LABEL: expand14:
|
||||
; KNL64: # %bb.0:
|
||||
; KNL64-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,3,0,0]
|
||||
; KNL64-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1]
|
||||
; KNL64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3]
|
||||
; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3]
|
||||
; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7]
|
||||
; KNL64-NEXT: retq
|
||||
;
|
||||
|
|
@ -528,10 +527,9 @@ define <8 x float> @expand14(<4 x float> %a) {
|
|||
;
|
||||
; KNL32-LABEL: expand14:
|
||||
; KNL32: # %bb.0:
|
||||
; KNL32-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,3,0,0]
|
||||
; KNL32-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1]
|
||||
; KNL32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3]
|
||||
; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3]
|
||||
; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7]
|
||||
; KNL32-NEXT: retl
|
||||
%addV = fadd <4 x float> <float 0.0,float 1.0,float 2.0,float 0.0> , <float 0.0,float 1.0,float 2.0,float 0.0>
|
||||
|
|
|
|||
|
|
@ -985,9 +985,8 @@ define internal fastcc <8 x float> @PR34577(<8 x float> %inp0, <8 x float> %inp1
|
|||
;
|
||||
; X32-AVX512-LABEL: PR34577:
|
||||
; X32-AVX512: # %bb.0: # %entry
|
||||
; X32-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = <1,u,u,u,2,u,5,0>
|
||||
; X32-AVX512-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
||||
; X32-AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
|
||||
; X32-AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3]
|
||||
; X32-AVX512-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
|
||||
; X32-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = <u,u,7,2,u,u,3,2>
|
||||
; X32-AVX512-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
||||
|
|
@ -1006,9 +1005,8 @@ define internal fastcc <8 x float> @PR34577(<8 x float> %inp0, <8 x float> %inp1
|
|||
;
|
||||
; X64-AVX512-LABEL: PR34577:
|
||||
; X64-AVX512: # %bb.0: # %entry
|
||||
; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = <1,u,u,u,2,u,5,0>
|
||||
; X64-AVX512-NEXT: vpermps %ymm0, %ymm2, %ymm0
|
||||
; X64-AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
|
||||
; X64-AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,1,3]
|
||||
; X64-AVX512-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7]
|
||||
; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = <u,u,7,2,u,u,3,2>
|
||||
; X64-AVX512-NEXT: vpermps %ymm1, %ymm2, %ymm1
|
||||
|
|
|
|||
|
|
@ -237,8 +237,6 @@ define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
|
|||
; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||
; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSE1-NEXT: xorps %xmm2, %xmm2
|
||||
; SSE1-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
|
||||
; SSE1-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE1-NEXT: retq
|
||||
|
|
@ -258,8 +256,6 @@ define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
|
|||
; SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||
; SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSE1-NEXT: xorps %xmm2, %xmm2
|
||||
; SSE1-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; SSE1-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE1-NEXT: retq
|
||||
%a = load <2 x float>, <2 x float>* %ptr
|
||||
|
|
|
|||
|
|
@ -710,7 +710,7 @@ define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) {
|
|||
; AVX512F-NEXT: kmovw %edi, %k1
|
||||
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
|
||||
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [9,6,1,0,3,7,7,1]
|
||||
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,18446744073709551615,18446744073709551615,0,0]
|
||||
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,0,0,0,0]
|
||||
; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm2
|
||||
; AVX512F-NEXT: vptestmq %zmm2, %zmm2, %k0
|
||||
; AVX512F-NEXT: kmovw %k0, %eax
|
||||
|
|
|
|||
|
|
@ -54,61 +54,19 @@ entry:
|
|||
}
|
||||
|
||||
define <8 x i32> @trunc8i64_8i32_ashr(<8 x i64> %a) {
|
||||
; SSE2-LABEL: trunc8i64_8i32_ashr:
|
||||
; SSE2: # %bb.0: # %entry
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,3,2,3]
|
||||
; SSE2-NEXT: psrad $31, %xmm3
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
|
||||
; SSE2-NEXT: psrad $31, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm3[0,2]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm4[0,2]
|
||||
; SSE2-NEXT: movaps %xmm2, %xmm1
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: trunc8i64_8i32_ashr:
|
||||
; SSSE3: # %bb.0: # %entry
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,3,2,3]
|
||||
; SSSE3-NEXT: psrad $31, %xmm3
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
|
||||
; SSSE3-NEXT: psrad $31, %xmm1
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm3[0,2]
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm4[0,2]
|
||||
; SSSE3-NEXT: movaps %xmm2, %xmm1
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: trunc8i64_8i32_ashr:
|
||||
; SSE41: # %bb.0: # %entry
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
|
||||
; SSE41-NEXT: psrad $31, %xmm3
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0,1],xmm3[2,3],xmm4[4,5],xmm3[6,7]
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
|
||||
; SSE41-NEXT: psrad $31, %xmm1
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm4[0,1],xmm1[2,3],xmm4[4,5],xmm1[6,7]
|
||||
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
|
||||
; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[0,2]
|
||||
; SSE41-NEXT: movaps %xmm2, %xmm1
|
||||
; SSE41-NEXT: retq
|
||||
; SSE-LABEL: trunc8i64_8i32_ashr:
|
||||
; SSE: # %bb.0: # %entry
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm3[1,3]
|
||||
; SSE-NEXT: movaps %xmm2, %xmm1
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: trunc8i64_8i32_ashr:
|
||||
; AVX1: # %bb.0: # %entry
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpsrad $31, %xmm2, %xmm3
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; AVX1-NEXT: vpsrad $31, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7]
|
||||
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[0,2]
|
||||
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[0,2]
|
||||
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
|
||||
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm2[1,3]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
|
|
|
|||
Loading…
Reference in New Issue