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[ARM] Reject CSEL instructions with invalid operands 

Summary:
According to the Armv8.1-M manual CSEL, CSINC, CSINV and CSNEG are
"constrained unpredictable" when SP is used as the source register Rn.

The assembler should diagnose this case.

Reviewers: momchil.velikov, dmgreen, ostannard, simon_tatham, t.p.northover

Reviewed By: ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65505

llvm-svn: 367433
This commit is contained in:
Mikhail Maltsev 2019-07-31 14:22:45 +00:00
parent 64d7af09f5
commit 806231ecc3
3 changed files with 31 additions and 14 deletions
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2
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -5235,7 +5235,7 @@ def t2LoopEnd :
} // end isNotDuplicable
class CS<string iname, bits<4> opcode, list<dag> pattern=[]>
: V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
: V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
bits<4> Rd;
bits<4> Rm;

18
llvm/test/MC/ARM/thumbv8.1m.s
View File

@ -1117,6 +1117,24 @@ csinv lr, r2, r2, mi
# CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
csel r0, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
csel sp, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinc r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinv r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csneg r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, r0, sp, eq
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it eq
csel r0, r0, r1, eq

25
llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
View File

@ -42,8 +42,7 @@
# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
[0x5d,0xea,0x02,0x80]
# CHECK: csel r0, sp, r2, eq @ encoding: [0x5d,0xea,0x02,0x80]
# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x51,0xea,0x0d,0x80]
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
@ -52,37 +51,37 @@
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x22 0x9e]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x47 0x9e]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x3c 0xae]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x3a 0xbe]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x7b 0x89]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x1f 0x9e]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x3f 0xae]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0xd7 0x9e]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x2f 0xae]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x42 0xae]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x5d 0xea 0x7b 0xbe]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
[0x52 0xea 0x22 0x9d]
# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding