forked from OSchip/llvm-project
ARM: lower fpowi appropriately for Windows ARM
This handles the last case of the builtin function calls that we would
generate code which differed from Microsoft's ABI. Rather than
generating a call to `__pow{d,s}i2` we now promote the parameter to a
float or double and invoke `powf` or `pow` instead.
Addresses PR30825!
llvm-svn: 286082
This commit is contained in:
Saleem Abdulrasool
parent
f8d38d11b9
commit
804e12eeb5
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@ -1017,6 +1017,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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}
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if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
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for (auto &VT : {MVT::f32, MVT::f64})
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setOperationAction(ISD::FPOWI, VT, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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@ -7525,6 +7529,58 @@ static void ReplaceCMP_SWAP_64Results(SDNode *N,
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Results.push_back(SDValue(CmpSwap, 2));
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}
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static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget,
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SelectionDAG &DAG) {
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const auto &TLI = DAG.getTargetLoweringInfo();
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assert(Subtarget.getTargetTriple().isOSMSVCRT() &&
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"Custom lowering is MSVCRT specific!");
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SDLoc dl(Op);
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SDValue Val = Op.getOperand(0);
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MVT Ty = Val->getSimpleValueType(0);
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SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, dl, Ty, Op.getOperand(1));
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SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow",
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TLI.getPointerTy(DAG.getDataLayout()));
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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Entry.Node = Val;
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Entry.Ty = Val.getValueType().getTypeForEVT(*DAG.getContext());
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Entry.isZExt = true;
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Args.push_back(Entry);
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Entry.Node = Exponent;
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Entry.Ty = Exponent.getValueType().getTypeForEVT(*DAG.getContext());
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Entry.isZExt = true;
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Args.push_back(Entry);
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Type *LCRTy = Val.getValueType().getTypeForEVT(*DAG.getContext());
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// In the in-chain to the call is the entry node If we are emitting a
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// tailcall, the chain will be mutated if the node has a non-entry input
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// chain.
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SDValue InChain = DAG.getEntryNode();
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SDValue TCChain = InChain;
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const auto *F = DAG.getMachineFunction().getFunction();
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bool IsTC = TLI.isInTailCallPosition(DAG, Op.getNode(), TCChain) &&
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F->getReturnType() == LCRTy;
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if (IsTC)
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InChain = TCChain;
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl)
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.setChain(InChain)
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.setCallee(CallingConv::ARM_AAPCS_VFP, LCRTy, Callee, std::move(Args))
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.setTailCall(IsTC);
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std::pair<SDValue, SDValue> CI = TLI.LowerCallTo(CLI);
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// Return the chain (the DAG root) if it is a tail call
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return !CI.second.getNode() ? DAG.getRoot() : CI.first;
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}
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SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Don't know how to custom lower this!");
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@ -7611,6 +7667,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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llvm_unreachable("Don't know how to custom lower this!");
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case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
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case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
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case ISD::FPOWI: return LowerFPOWI(Op, *Subtarget, DAG);
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case ARMISD::WIN__DBZCHK: return SDValue();
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}
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}
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@ -0,0 +1,57 @@
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; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
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declare double @llvm.powi.f64(double, i32)
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declare float @llvm.powi.f32(float, i32)
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define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64(double %d, i32 %i)
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ret double %0
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}
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; CHECK-LABEL: d:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32(float %f, i32 %i)
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ret float %0
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}
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; CHECK-LABEL: f:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64(double %d, i32 %i)
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%conv = fptrunc double %0 to float
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ret float %conv
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}
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; CHECK-LABEL: g:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: bl pow
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; CHECK-NOT: bl __powidf2
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; CHECK-NEXT: vcvt.f32.f64 s0, d0
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define arm_aapcs_vfpcc double @h(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32(float %f, i32 %i)
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%conv = fpext float %0 to double
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ret double %conv
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}
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; CHECK-LABEL: h:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: bl powf
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; CHECK-NOT: bl __powisf2
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; CHECK-NEXT: vcvt.f64.f32 d0, s0
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