forked from OSchip/llvm-project
[ARM][MVE] Allow tail predication for strides !=1 with gather/scatters
If gather/scatters are enabled, ARMTargetTransformInfo now allows tail predication for loops with a much wider range of strides, up to anything that is loop invariant. Differential Revision: https://reviews.llvm.org/D85410
This commit is contained in:
Anna Welker
parent
105151ca56
commit
8048068c3e
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@ -143,7 +143,7 @@ static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
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cl::desc("Maximum size of ALL constants to promote into a constant pool"),
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cl::init(128));
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static cl::opt<unsigned>
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cl::opt<unsigned>
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MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
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cl::desc("Maximum interleave factor for MVE VLDn to generate."),
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cl::init(2));
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@ -52,6 +52,8 @@ extern cl::opt<TailPredication::Mode> EnableTailPredication;
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extern cl::opt<bool> EnableMaskedGatherScatters;
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extern cl::opt<unsigned> MVEMaxSupportedInterleaveFactor;
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/// Convert a vector load intrinsic into a simple llvm load instruction.
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/// This is beneficial when the underlying object being addressed comes
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/// from a constant, since we get constant-folding for free.
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@ -1643,7 +1645,6 @@ static bool canTailPredicateLoop(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
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PredicatedScalarEvolution PSE = LAI->getPSE();
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SmallVector<Instruction *, 16> LoadStores;
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int ICmpCount = 0;
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int Stride = 0;
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for (BasicBlock *BB : L->blocks()) {
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for (Instruction &I : BB->instructionsWithoutDebug()) {
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@ -1662,22 +1663,38 @@ static bool canTailPredicateLoop(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
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LLVM_DEBUG(dbgs() << "Unsupported Type: "; T->dump());
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return false;
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}
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if (isa<StoreInst>(I) || isa<LoadInst>(I)) {
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Value *Ptr = isa<LoadInst>(I) ? I.getOperand(0) : I.getOperand(1);
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int64_t NextStride = getPtrStride(PSE, Ptr, L);
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// TODO: for now only allow consecutive strides of 1. We could support
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// other strides as long as it is uniform, but let's keep it simple for
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// now.
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if (Stride == 0 && NextStride == 1) {
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Stride = NextStride;
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if (NextStride == 1) {
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// TODO: for now only allow consecutive strides of 1. We could support
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// other strides as long as it is uniform, but let's keep it simple
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// for now.
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continue;
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}
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if (Stride != NextStride) {
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LLVM_DEBUG(dbgs() << "Different strides found, can't "
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"tail-predicate\n.");
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} else if (NextStride == -1 ||
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(NextStride == 2 && MVEMaxSupportedInterleaveFactor >= 2) ||
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(NextStride == 4 && MVEMaxSupportedInterleaveFactor >= 4)) {
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LLVM_DEBUG(dbgs()
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<< "Consecutive strides of 2 found, vld2/vstr2 can't "
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"be tail-predicated\n.");
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return false;
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// TODO: don't tail predicate if there is a reversed load?
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} else if (EnableMaskedGatherScatters) {
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// Gather/scatters do allow loading from arbitrary strides, at
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// least if they are loop invariant.
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// TODO: Loop variant strides should in theory work, too, but
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// this requires further testing.
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const SCEV *PtrScev =
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replaceSymbolicStrideSCEV(PSE, llvm::ValueToValueMap(), Ptr);
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if (auto AR = dyn_cast<SCEVAddRecExpr>(PtrScev)) {
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const SCEV *Step = AR->getStepRecurrence(*PSE.getSE());
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if (PSE.getSE()->isLoopInvariant(Step, L))
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continue;
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}
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}
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LLVM_DEBUG(dbgs() << "Bad stride found, can't "
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"tail-predicate\n.");
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return false;
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}
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}
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}
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@ -0,0 +1,391 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-vectorize -force-vector-width=4 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat -tail-predication=force-enabled -S %s -o - | FileCheck %s
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define void @test_stride1_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
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; CHECK-LABEL: @test_stride1_4i32(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT2]], <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[TMP0]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[BROADCAST_SPLAT:%.*]], i32 0
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP0]], i32 [[TMP4]])
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
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; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP6]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
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; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_LOAD]]
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP0]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 0
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; CHECK-NEXT: [[TMP10:%.*]] = bitcast i32* [[TMP9]] to <4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP7]], <4 x i32>* [[TMP10]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
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; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%mul = mul nuw nsw i32 %i.023, 1
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%add5 = add nuw nsw i32 %mul, 2
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%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
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%0 = load i32, i32* %arrayidx6, align 4
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%add7 = add nsw i32 5, %0
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%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
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store i32 %add7, i32* %arrayidx9, align 4
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%inc = add nuw nsw i32 %i.023, 1
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%exitcond.not = icmp eq i32 %inc, %n
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br i1 %exitcond.not, label %end, label %for.body
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end: ; preds = %end, %entry
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ret void
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}
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define void @test_stride-1_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
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; CHECK-LABEL: @test_stride-1_4i32(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP9:%.*]] = mul nuw nsw i32 [[TMP8]], -1
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; CHECK-NEXT: [[TMP10:%.*]] = add nuw nsw i32 [[TMP9]], 2
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP10]]
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i32 0
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i32 -3
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; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP13]] to <4 x i32>*
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP14]], align 4
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; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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; CHECK-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[REVERSE]]
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP8]]
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 0
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; CHECK-NEXT: [[TMP18:%.*]] = bitcast i32* [[TMP17]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP15]], <4 x i32>* [[TMP18]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
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; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !4
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%mul = mul nuw nsw i32 %i.023, -1
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%add5 = add nuw nsw i32 %mul, 2
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%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
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%0 = load i32, i32* %arrayidx6, align 4
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%add7 = add nsw i32 5, %0
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%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
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store i32 %add7, i32* %arrayidx9, align 4
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%inc = add nuw nsw i32 %i.023, 1
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%exitcond.not = icmp eq i32 %inc, %n
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br i1 %exitcond.not, label %end, label %for.body
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end: ; preds = %end, %entry
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ret void
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}
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define void @test_stride2_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
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;
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; CHECK-LABEL: @test_stride2_4i32(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP3:%.*]] = mul nuw nsw i32 [[TMP2]], 2
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 2
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP5]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <8 x i32>*
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, <8 x i32>* [[TMP7]], align 4
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[STRIDED_VEC]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP2]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
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; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !6
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%mul = mul nuw nsw i32 %i.023, 2
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%add5 = add nuw nsw i32 %mul, 2
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%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
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%0 = load i32, i32* %arrayidx6, align 4
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%add7 = add nsw i32 5, %0
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%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
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store i32 %add7, i32* %arrayidx9, align 4
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%inc = add nuw nsw i32 %i.023, 1
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%exitcond.not = icmp eq i32 %inc, %n
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br i1 %exitcond.not, label %end, label %for.body
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end: ; preds = %end, %entry
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ret void
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}
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define void @test_stride3_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
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; CHECK-LABEL: @test_stride3_4i32(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 3
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; CHECK-NEXT: [[TMP4:%.*]] = mul nuw nsw <4 x i32> [[VEC_IND]], <i32 3, i32 3, i32 3, i32 3>
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i32> [[TMP4]], <i32 2, i32 2, i32 2, i32 2>
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], <4 x i32> [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[BROADCAST_SPLAT:%.*]], i32 0
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP0]], i32 [[TMP7]])
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; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP6]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
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; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_GATHER]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP0]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
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; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !8
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%mul = mul nuw nsw i32 %i.023, 3
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%add5 = add nuw nsw i32 %mul, 2
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%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
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%0 = load i32, i32* %arrayidx6, align 4
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%add7 = add nsw i32 5, %0
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%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
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store i32 %add7, i32* %arrayidx9, align 4
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%inc = add nuw nsw i32 %i.023, 1
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%exitcond.not = icmp eq i32 %inc, %n
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br i1 %exitcond.not, label %end, label %for.body
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end: ; preds = %end, %entry
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ret void
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}
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define void @test_stride4_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
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; CHECK-LABEL: @test_stride4_4i32(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 3
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; CHECK-NEXT: [[TMP4:%.*]] = mul nuw nsw <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i32> [[TMP4]], <i32 2, i32 2, i32 2, i32 2>
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], <4 x i32> [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[BROADCAST_SPLAT:%.*]], i32 0
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP0]], i32 [[TMP7]])
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; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP6]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_GATHER]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
|
||||
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
|
||||
; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP10:!llvm.loop !.*]]
|
||||
;
|
||||
entry:
|
||||
br label %for.body
|
||||
for.body: ; preds = %for.body.preheader, %for.body
|
||||
%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%mul = mul nuw nsw i32 %i.023, 4
|
||||
%add5 = add nuw nsw i32 %mul, 2
|
||||
%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
|
||||
%0 = load i32, i32* %arrayidx6, align 4
|
||||
%add7 = add nsw i32 5, %0
|
||||
%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
|
||||
store i32 %add7, i32* %arrayidx9, align 4
|
||||
%inc = add nuw nsw i32 %i.023, 1
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %end, label %for.body
|
||||
end: ; preds = %end, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_stride_loopinvar_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n, i32 %stride) {
|
||||
; CHECK-LABEL: @test_stride_loopinvar_4i32(
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT2]], <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i32 [[TMP1]], [[STRIDE:%.*]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 2
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[BROADCAST_SPLAT]], i32 0
|
||||
; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP1]], i32 [[TMP5]])
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 0
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <4 x i32>*
|
||||
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP7]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> undef)
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_LOAD]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
|
||||
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
|
||||
; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP12:!llvm.loop !.*]]
|
||||
;
|
||||
entry:
|
||||
br label %for.body
|
||||
for.body: ; preds = %for.body.preheader, %for.body
|
||||
%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%mul = mul nuw nsw i32 %i.023, %stride
|
||||
%add5 = add nuw nsw i32 %mul, 2
|
||||
%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
|
||||
%0 = load i32, i32* %arrayidx6, align 4
|
||||
%add7 = add nsw i32 5, %0
|
||||
%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
|
||||
store i32 %add7, i32* %arrayidx9, align 4
|
||||
%inc = add nuw nsw i32 %i.023, 1
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %end, label %for.body
|
||||
end: ; preds = %end, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_stride_noninvar_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
|
||||
; CHECK-LABEL: @test_stride_noninvar_4i32(
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_IND2:%.*]] = phi <4 x i32> [ <i32 3, i32 11, i32 19, i32 27>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT3:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = mul nuw nsw <4 x i32> [[VEC_IND]], [[VEC_IND2]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw <4 x i32> [[TMP5]], <i32 2, i32 2, i32 2, i32 2>
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], <4 x i32> [[TMP6]]
|
||||
; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP7]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_GATHER]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
|
||||
; CHECK-NEXT: store <4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], align 4
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT3]] = add <4 x i32> [[VEC_IND2]], <i32 32, i32 32, i32 32, i32 32>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
|
||||
; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP14:!llvm.loop !.*]]
|
||||
;
|
||||
entry:
|
||||
br label %for.body
|
||||
for.body: ; preds = %for.body.preheader, %for.body
|
||||
%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%stride = phi i32 [ %next.stride, %for.body ], [ 3, %entry ]
|
||||
%mul = mul nuw nsw i32 %i.023, %stride
|
||||
%add5 = add nuw nsw i32 %mul, 2
|
||||
%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
|
||||
%0 = load i32, i32* %arrayidx6, align 4
|
||||
%add7 = add nsw i32 5, %0
|
||||
%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
|
||||
store i32 %add7, i32* %arrayidx9, align 4
|
||||
%inc = add nuw nsw i32 %i.023, 1
|
||||
%next.stride = add nuw nsw i32 %stride, 8
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %end, label %for.body
|
||||
end: ; preds = %end, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_stride_noninvar2_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n) {
|
||||
; CHECK-LABEL: @test_stride_noninvar2_4i32(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
|
||||
; CHECK: for.body:
|
||||
; CHECK-NEXT: [[I_023:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
|
||||
; CHECK-NEXT: [[STRIDE:%.*]] = phi i32 [ [[NEXT_STRIDE:%.*]], [[FOR_BODY]] ], [ 3, [[ENTRY]] ]
|
||||
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[I_023]], [[STRIDE]]
|
||||
; CHECK-NEXT: [[ADD5:%.*]] = add nuw nsw i32 [[MUL]], 2
|
||||
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[ADD5]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
|
||||
; CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 5, [[TMP0]]
|
||||
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[I_023]]
|
||||
; CHECK-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX9]], align 4
|
||||
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_023]], 1
|
||||
; CHECK-NEXT: [[NEXT_STRIDE]] = mul nuw nsw i32 [[STRIDE]], 8
|
||||
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[N:%.*]]
|
||||
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[END:%.*]], label [[FOR_BODY]]
|
||||
; CHECK: end:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %for.body
|
||||
for.body: ; preds = %for.body.preheader, %for.body
|
||||
%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%stride = phi i32 [ %next.stride, %for.body ], [ 3, %entry ]
|
||||
%mul = mul nuw nsw i32 %i.023, %stride
|
||||
%add5 = add nuw nsw i32 %mul, 2
|
||||
%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
|
||||
%0 = load i32, i32* %arrayidx6, align 4
|
||||
%add7 = add nsw i32 5, %0
|
||||
%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
|
||||
store i32 %add7, i32* %arrayidx9, align 4
|
||||
%inc = add nuw nsw i32 %i.023, 1
|
||||
%next.stride = mul nuw nsw i32 %stride, 8
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %end, label %for.body
|
||||
end: ; preds = %end, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_stride_noninvar3_4i32(i32* readonly %data, i32* noalias nocapture %dst, i32 %n, i32 %x) {
|
||||
; CHECK-LABEL: @test_stride_noninvar3_4i32(
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY:%.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[VEC_IND4:%.*]] = phi <4 x i32> [ [[INDUCTION:%.*]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT5:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw <4 x i32> [[VEC_IND]], [[VEC_IND4]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw <4 x i32> [[TMP7]], <i32 2, i32 2, i32 2, i32 2>
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], <4 x i32> [[TMP8]]
|
||||
; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP9]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_GATHER]]
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i32 0
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP12]] to <4 x i32>*
|
||||
; CHECK-NEXT: store <4 x i32> [[TMP10]], <4 x i32>* [[TMP13]], align 4
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT5]] = add <4 x i32> [[VEC_IND4]], [[DOTSPLAT3:%.*]]
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC:%.*]]
|
||||
; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP16:!llvm.loop !.*]]
|
||||
;
|
||||
entry:
|
||||
br label %for.body
|
||||
for.body: ; preds = %for.body.preheader, %for.body
|
||||
%i.023 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
||||
%stride = phi i32 [ %next.stride, %for.body ], [ 3, %entry ]
|
||||
%mul = mul nuw nsw i32 %i.023, %stride
|
||||
%add5 = add nuw nsw i32 %mul, 2
|
||||
%arrayidx6 = getelementptr inbounds i32, i32* %data, i32 %add5
|
||||
%0 = load i32, i32* %arrayidx6, align 4
|
||||
%add7 = add nsw i32 5, %0
|
||||
%arrayidx9 = getelementptr inbounds i32, i32* %dst, i32 %i.023
|
||||
store i32 %add7, i32* %arrayidx9, align 4
|
||||
%inc = add nuw nsw i32 %i.023, 1
|
||||
%next.stride = add nuw nsw i32 %stride, %x
|
||||
%exitcond.not = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond.not, label %end, label %for.body
|
||||
end: ; preds = %end, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
|
||||
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
|
||||
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
|
||||
Loading…
Reference in New Issue