forked from OSchip/llvm-project
[AArch64][GlobalISel] Select XRO addressing mode with wide immediates
Port the wide immediate case from AArch64DAGToDAGISel::SelectAddrModeXRO. If we have a wide immediate which can't be represented in an add, we can end up with code like this: ``` mov x0, imm add x1, base, x0 ldr x2, [x1, 0] ``` If we use the [base, xN] addressing mode instead, we can produce this: ``` mov x0, imm ldr x2, [base, x0] ``` This saves 0.4% code size on 7zip at -O3, and gives a geomean code size improvement of 0.1% on CTMark. Differential Revision: https://reviews.llvm.org/D84784
This commit is contained in:
Jessica Paquette
parent
766cb615a3
commit
7ff9575594
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@ -5083,11 +5083,59 @@ InstructionSelector::ComplexRendererFns
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AArch64InstructionSelector::selectAddrModeXRO(MachineOperand &Root,
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unsigned SizeInBytes) const {
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MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
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// If we have a constant offset, then we probably don't want to match a
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// register offset.
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if (isBaseWithConstantOffset(Root, MRI))
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if (!Root.isReg())
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return None;
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MachineInstr *PtrAdd =
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getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
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if (!PtrAdd)
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return None;
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// Check for an immediates which cannot be encoded in the [base + imm]
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// addressing mode, and can't be encoded in an add/sub. If this happens, we'll
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// end up with code like:
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//
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// mov x0, wide
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// add x1 base, x0
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// ldr x2, [x1, x0]
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//
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// In this situation, we can use the [base, xreg] addressing mode to save an
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// add/sub:
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//
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// mov x0, wide
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// ldr x2, [base, x0]
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auto ValAndVReg =
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getConstantVRegValWithLookThrough(PtrAdd->getOperand(2).getReg(), MRI);
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if (ValAndVReg) {
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unsigned Scale = Log2_32(SizeInBytes);
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int64_t ImmOff = ValAndVReg->Value;
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// Skip immediates that can be selected in the load/store addresing
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// mode.
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if (ImmOff % SizeInBytes == 0 && ImmOff >= 0 &&
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ImmOff < (0x1000 << Scale))
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return None;
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// Helper lambda to decide whether or not it is preferable to emit an add.
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auto isPreferredADD = [](int64_t ImmOff) {
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// Constants in [0x0, 0xfff] can be encoded in an add.
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if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
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return true;
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// Can it be encoded in an add lsl #12?
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if ((ImmOff & 0xffffffffff000fffLL) != 0x0LL)
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return false;
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// It can be encoded in an add lsl #12, but we may not want to. If it is
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// possible to select this as a single movz, then prefer that. A single
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// movz is faster than an add with a shift.
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return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
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(ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
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};
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// If the immediate can be encoded in a single add/sub, then bail out.
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if (isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
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return None;
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}
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// Try to fold shifts into the addressing mode.
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auto AddrModeFns = selectAddrModeShiftedExtendXReg(Root, SizeInBytes);
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@ -0,0 +1,211 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test using the xro addressing mode with immediates. This should be done for
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# wide constants which are preferably selected using a mov rather than an add.
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...
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---
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name: use_xro_cannot_encode_add_lsl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Check that we use the XRO addressing mode when the constant cannot be
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; represented using an add + lsl.
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;
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; cst = 0000000111000000
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; cst & 000fffffff000000 != 0
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;
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; CHECK-LABEL: name: use_xro_cannot_encode_add_lsl
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %cst:gpr64 = MOVi64imm 4580179968
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; CHECK: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 4580179968
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: use_xro_preferred_mov
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Check that we use the XRO addressing mode when the constant can be
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; represented using a single movk.
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;
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; cst = 000000000000f000
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; cst & 000fffffff000000 == 0
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; cst & ffffffffffff0fff != 0
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;
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; CHECK-LABEL: name: use_xro_preferred_mov
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 61440
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; CHECK: %cst:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 61440
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: use_xro_negative_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Check that this works even if we have a negative immediate.
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;
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; CHECK-LABEL: name: use_xro_negative_imm
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %cst:gpr64 = MOVi64imm -61440
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; CHECK: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 -61440
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: dont_use_xro_selectable_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Immediates that can be encoded in a LDRXui should be skipped.
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;
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; CHECK-LABEL: name: dont_use_xro_selectable_imm
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %load:gpr64 = LDRXui %copy, 2 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 16
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: dont_use_xro_selectable_negative_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Immediates that can be encoded in a LDRXui should be skipped.
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;
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; CHECK-LABEL: name: dont_use_xro_selectable_negative_imm
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %load:gpr64 = LDURXi %copy, -16 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 -16
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: dont_use_xro_zero
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Immediates that can be encoded in a LDRXui should be skipped.
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;
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; CHECK-LABEL: name: dont_use_xro_zero
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %load:gpr64 = LDRXui %copy, 0 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 0
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: dont_use_xro_in_range
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Check that we skip constants which can be encoded in an add.
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; 17 is in [0x0, 0xfff]
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;
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; CHECK-LABEL: name: dont_use_xro_in_range
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %load:gpr64 = LDURXi %copy, 17 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 17
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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...
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---
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name: dont_use_xro_add_lsl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; Check that we skip when we have an add with an lsl which cannot be
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; represented as a movk.
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;
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; cst = 0x0000000000111000
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; cst & 000fffffff000000 = 0
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; cst & ffffffffff00ffff != 0
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; cst & ffffffffffff0fff != 0
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;
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; CHECK-LABEL: name: dont_use_xro_add_lsl
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64 = COPY $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY %copy
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; CHECK: %addr:gpr64sp = ADDXri [[COPY]], 273, 12
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; CHECK: %load:gpr64 = LDRXui %addr, 0 :: (volatile load 8)
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; CHECK: RET_ReallyLR
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%copy:gpr(p0) = COPY $x0
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%cst:gpr(s64) = G_CONSTANT i64 1118208
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%addr:gpr(p0) = G_PTR_ADD %copy, %cst(s64)
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%load:gpr(s64) = G_LOAD %addr(p0) :: (volatile load 8)
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RET_ReallyLR
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