From 7fdd268b68068ba9a9e498a2b2e9e1939eecd53a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 16 May 2013 13:39:02 +0000 Subject: [PATCH] [SystemZ] Tweak register array comment llvm-svn: 182007 --- llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 1f70047db6be..3c9f0cb9db01 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -36,8 +36,11 @@ namespace SystemZMC { const int64_t CFAOffsetFromInitialSP = CallFrameSize; // Maps of asm register numbers to LLVM register numbers, with 0 indicating - // an invalid register. We don't use the register classes directly because - // they specify the allocation order. + // an invalid register. In principle we could use 32-bit and 64-bit register + // classes directly, provided that we relegated the GPR allocation order + // in SystemZRegisterInfo.td to an AltOrder and left the default order + // as %r0-%r15. It seems better to provide the same interface for + // all classes though. extern const unsigned GR32Regs[16]; extern const unsigned GR64Regs[16]; extern const unsigned GR128Regs[16];