[MC] Move the reciprocal throughput computation from TargetSchedModel to MCSchedModel.

The goal is to make the reciprocal throughput computation accessible through the
MCSchedModel interface. This is particularly important for llvm-mca because it
can only query the MCSchedModel interface.

No functional change intended.

Differential Revision: https://reviews.llvm.org/D44392

llvm-svn: 327420
This commit is contained in:
Andrea Di Biagio 2018-03-13 16:28:55 +00:00
parent b9f4b70f20
commit 7faea7cb53
3 changed files with 34 additions and 29 deletions

View File

@ -15,6 +15,7 @@
#ifndef LLVM_MC_MCSCHEDULE_H
#define LLVM_MC_MCSCHEDULE_H
#include "llvm/ADT/Optional.h"
#include "llvm/Support/DataTypes.h"
#include <cassert>
@ -231,6 +232,11 @@ struct MCSchedModel {
static int computeInstrLatency(const MCSubtargetInfo &STI,
const MCSchedClassDesc &SCDesc);
/// Returns the reciprocal throughput information from a MCSchedClassDesc.
static Optional<double>
getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCSchedClassDesc &SCDesc);
/// Returns the default initialized model.
static const MCSchedModel &GetDefaultSchedModel() { return Default; }
static const MCSchedModel Default;

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@ -347,38 +347,13 @@ getRThroughputFromItineraries(unsigned schedClass,
return Throughput;
}
static Optional<double>
getRThroughputFromInstrSchedModel(const MCSchedClassDesc *SCDesc,
const TargetSubtargetInfo *STI,
const MCSchedModel &SchedModel) {
Optional<double> Throughput;
for (const MCWriteProcResEntry *WPR = STI->getWriteProcResBegin(SCDesc),
*WEnd = STI->getWriteProcResEnd(SCDesc);
WPR != WEnd; ++WPR) {
if (WPR->Cycles) {
unsigned NumUnits =
SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits;
double Temp = NumUnits * 1.0 / WPR->Cycles;
Throughput = Throughput.hasValue()
? std::min(Throughput.getValue(), Temp)
: Temp;
}
}
if (Throughput.hasValue())
// We need reciprocal throughput that's why we return such value.
return 1 / Throughput.getValue();
return Throughput;
}
Optional<double>
TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const {
if (hasInstrItineraries())
return getRThroughputFromItineraries(MI->getDesc().getSchedClass(),
getInstrItineraries());
if (hasInstrSchedModel())
return getRThroughputFromInstrSchedModel(resolveSchedClass(MI), STI,
SchedModel);
return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
return Optional<double>();
}
@ -388,9 +363,9 @@ TargetSchedModel::computeInstrRThroughput(unsigned Opcode) const {
if (hasInstrItineraries())
return getRThroughputFromItineraries(SchedClass, getInstrItineraries());
if (hasInstrSchedModel()) {
const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
if (SCDesc->isValid() && !SCDesc->isVariant())
return getRThroughputFromInstrSchedModel(SCDesc, STI, SchedModel);
const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
if (SCDesc.isValid() && !SCDesc.isVariant())
return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
}
return Optional<double>();
}

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@ -49,3 +49,27 @@ int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
}
return Latency;
}
Optional<double>
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCSchedClassDesc &SCDesc) {
Optional<double> Throughput;
const MCSchedModel &SchedModel = STI.getSchedModel();
for (const MCWriteProcResEntry *WPR = STI.getWriteProcResBegin(&SCDesc),
*WEnd = STI.getWriteProcResEnd(&SCDesc);
WPR != WEnd; ++WPR) {
if (WPR->Cycles) {
unsigned NumUnits =
SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits;
double Temp = NumUnits * 1.0 / WPR->Cycles;
Throughput =
Throughput.hasValue() ? std::min(Throughput.getValue(), Temp) : Temp;
}
}
if (Throughput.hasValue())
return 1 / Throughput.getValue();
return Throughput;
}