forked from OSchip/llvm-project
[DAGCombiner] Distribute TRUNC through AND in rotation amount
This is already done for shifts. Allow it for rotations as well. E.g.: (rotl:i32 x, (trunc (and y, 31))) -> (rotl:i32 x, (and (trunc y), 31)) Use the newly factored-out distributeTruncateThroughAnd. With this patch and some X86.td tweaks we should be able to remove redundant masking of the rotation amount like in the example above. HW implicitly performs this masking. The testcase will be added as part of the X86 patch. llvm-svn: 203316
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@ -229,6 +229,7 @@ namespace {
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SDValue visitSHL(SDNode *N);
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SDValue visitSRA(SDNode *N);
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SDValue visitSRL(SDNode *N);
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SDValue visitRotate(SDNode *N);
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SDValue visitCTLZ(SDNode *N);
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SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
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SDValue visitCTTZ(SDNode *N);
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@ -1194,6 +1195,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::SHL: return visitSHL(N);
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case ISD::SRA: return visitSRA(N);
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case ISD::SRL: return visitSRL(N);
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case ISD::ROTR:
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case ISD::ROTL: return visitRotate(N);
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case ISD::CTLZ: return visitCTLZ(N);
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case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
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case ISD::CTTZ: return visitCTTZ(N);
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@ -3899,6 +3902,19 @@ SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
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return SDValue();
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}
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SDValue DAGCombiner::visitRotate(SDNode *N) {
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// fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
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if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
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N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
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SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
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if (NewOp1.getNode())
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return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
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N->getOperand(0), NewOp1);
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}
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return SDValue();
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}
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SDValue DAGCombiner::visitSHL(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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