forked from OSchip/llvm-project
[TableGen] [Docs] Add lldb-tblgen to command guide; add 4 guide stubs
Differential Revision: https://reviews.llvm.org/D99605
This commit is contained in:
Paul C. Anagnostopoulos
parent
d3b74dc1e4
commit
7f7f5e2543
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clang-tblgen - Description to C++ Code for Clang
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================================================
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.. program:: clang-tblgen
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SYNOPSIS
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--------
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:program:`clang-tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`clang-tblgen` is a program that translates compiler-related target
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for writing
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parts of the compiler.
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Please see :doc:`tblgen Family - Target Description to C++ Code<./tblgen>`
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for a description of the *filename* argument and options, including the
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options common to all :program:`*-tblgen` programs.
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@ -72,6 +72,10 @@ Developer Tools
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FileCheck
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FileCheck
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tblgen
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tblgen
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clang-tblgen
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lldb-tblgen
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llvm-tblgen
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mlir-tblgen
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lit
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lit
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llvm-exegesis
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llvm-exegesis
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llvm-locstats
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llvm-locstats
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lldb-tblgen - Description to C++ Code for LLDB
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==============================================
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.. program:: lldb-tblgen
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SYNOPSIS
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--------
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:program:`lldb-tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`lldb-tblgen` is a program that translates compiler-related target
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for writing
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parts of the compiler.
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Please see :doc:`tblgen Family - Target Description to C++ Code<./tblgen>`
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for a description of the *filename* argument and options, including the
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options common to all :program:`*-tblgen` programs.
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llvm-tblgen - Target Description to C++ Code for LLVM
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=====================================================
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.. program:: llvm-tblgen
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SYNOPSIS
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--------
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:program:`llvm-tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`llvm-tblgen` is a program that translates compiler-related target
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for writing
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parts of the compiler.
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Please see :doc:`tblgen Family - Target Description to C++ Code<./tblgen>`
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for a description of the *filename* argument and options, including the
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options common to all :program:`*-tblgen` programs.
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mlir-tblgen - Description to C++ Code for MLIR
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==============================================
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.. program:: mlir-tblgen
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SYNOPSIS
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--------
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:program:`mlir-tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`mlir-tblgen` is a program that translates compiler-related target
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for writing
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parts of the compiler.
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Please see :doc:`tblgen Family - Target Description to C++ Code<./tblgen>`
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for a description of the *filename* argument and options, including the
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options common to all :program:`*-tblgen` programs.
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xxx-tblgen - Target Description to C++ Code
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tblgen Family - Description to C++ Code
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===========================================
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=======================================
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.. program:: tblgen
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.. program:: tblgen
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SYNOPSIS
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SYNOPSIS
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--------
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--------
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:program:`xxx-tblgen` [*options*] [*filename*]
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:program:`clang-tblgen` [*options*] [*filename*]
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:program:`lldb-tblgen` [*options*] [*filename*]
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:program:`llvm-tblgen` [*options*] [*filename*]
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:program:`mlir-tblgen` [*options*] [*filename*]
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DESCRIPTION
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DESCRIPTION
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-----------
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-----------
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:program:`xxx-tblgen` is a family of programs that translates target
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:program:`*-tblgen` is a family of programs that translates target
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description (``.td``) files into C++ code and other output formats. Most
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for
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users of LLVM will not need to use this program. It is used only for
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writing parts of the compiler or LLVM target backends.
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writing parts of the compiler, debugger, and LLVM target backends.
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The details of the input and output of :program:`xxx-tblgen` is beyond the
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The details of the input and output of :program:`*-tblgen` is beyond the
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scope of this short introduction; please see the :doc:`TableGen Overview
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scope of this short introduction; please see the :doc:`TableGen Overview
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<../TableGen/index>` for an introduction and for references to additional
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<../TableGen/index>` for an introduction and for references to additional
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TableGen documents.
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TableGen documents.
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@ -70,7 +76,7 @@ General Options
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.. option:: -o filename
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.. option:: -o filename
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Specify the output file name. If ``filename`` is ``-``, then
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Specify the output file name. If ``filename`` is ``-``, then
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:program:`xxx-tblgen` sends its output to standard output.
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:program:`*-tblgen` sends its output to standard output.
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.. option:: -print-records
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.. option:: -print-records
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@ -97,217 +103,6 @@ General Options
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Write the output file only if it is new or has changed.
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Write the output file only if it is new or has changed.
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llvm-tblgen Options
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~~~~~~~~~~~~~~~~~~~
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.. option:: -gen-asm-matcher
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Generate assembly instruction matcher.
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.. option:: -match-prefix=prefix
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Make -gen-asm-matcher match only instructions with the given *prefix*.
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.. option:: -gen-asm-parser
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Generate assembly instruction parser.
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.. option:: -asmparsernum=n
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Make -gen-asm-parser emit assembly parser number *n*.
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.. option:: -gen-asm-writer
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Generate assembly writer.
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.. option:: -asmwriternum=n
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Make -gen-asm-writer emit assembly writer number *n*.
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.. option:: -gen-attrs
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Generate attributes.
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.. option:: -gen-automata
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Generate generic automata.
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.. option:: -gen-callingconv
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Generate calling convention descriptions.
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.. option:: -gen-compress-inst-emitter
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Generate RISC-V compressed instructions.
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.. option:: -gen-ctags
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Generate ctags-compatible index.
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.. option:: -gen-dag-isel
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Generate a DAG (directed acyclic graph) instruction selector.
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.. option:: -instrument-coverage
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Make -gen-dag-isel generate tables to help identify the patterns matched.
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.. option:: -omit-comments
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Make -gen-dag-isel omit comments. The default is false.
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.. option:: -gen-dfa-packetizer
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Generate DFA Packetizer for VLIW targets.
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.. option:: -gen-directive-decl
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Generate directive related declaration code (header file).
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.. option:: -gen-directive-gen
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Generate directive related implementation code part.
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.. option:: -gen-directive-impl
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Generate directive related implementation code.
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.. option:: -gen-disassembler
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Generate disassembler.
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.. option:: -gen-emitter
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Generate machine code emitter.
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.. option:: -gen-exegesis
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Generate llvm-exegesis tables.
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.. option:: -gen-fast-isel
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Generate a "fast" instruction selector.
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.. option:: -gen-global-isel
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Generate GlobalISel selector.
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.. option:: -gisel-coverage-file=filename
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Specify the file from which to retrieve coverage information.
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.. option:: -instrument-gisel-coverage
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Make -gen-global-isel generate coverage instrumentation.
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.. option:: -optimize-match-table
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Make -gen-global-isel generate an optimized version of the match table.
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.. option:: -warn-on-skipped-patterns
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Make -gen-global-isel explain why a pattern was skipped for inclusion.
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.. option:: -gen-global-isel-combiner
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Generate GlobalISel combiner.
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.. option:: -combiners=list
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Make -gen-global-isel-combiner emit the specified combiners.
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.. option:: -gicombiner-show-expansions
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Make -gen-global-isel-combiner use C++ comments to indicate occurrences
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of code expansion.
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.. option:: -gicombiner-stop-after-build
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Make -gen-global-isel-combiner stop processing after building the match tree.
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.. option:: -gicombiner-stop-after-parse
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Make -gen-global-isel-combiner stop processing after parsing rules
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and dump state.
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.. option:: -gen-instr-info
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Generate instruction descriptions.
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.. option:: -gen-instr-docs
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Generate instruction documentation.
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.. option:: -gen-intrinsic-enums
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Generate intrinsic enums.
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.. option:: -intrinsic-prefix=prefix
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Make -gen-intrinsic-enums generate intrinsics with this target *prefix*.
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.. option:: -gen-intrinsic-impl
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Generate intrinsic information.
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.. option:: -gen-opt-parser-defs
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Generate options definitions.
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.. option:: -gen-opt-rst
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Generate option RST.
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.. option:: -gen-pseudo-lowering
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Generate pseudo instruction lowering.
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.. option:: -gen-register-bank
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Generate register bank descriptions.
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.. option:: -gen-register-info
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Generate registers and register classes info.
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.. option:: -register-info-debug
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Make -gen-register-info dump register information for debugging.
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.. option:: -gen-searchable-tables
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Generate generic searchable tables. See :doc:`TableGen BackEnds <../TableGen/BackEnds>`
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for a detailed description.
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.. option:: -gen-subtarget
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Generate subtarget enumerations.
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.. option:: -gen-x86-EVEX2VEX-tables
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Generate X86 EVEX to VEX compress tables.
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.. option:: -gen-x86-fold-tables
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Generate X86 fold tables.
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.. option:: -long-string-literals
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When emitting large string tables, prefer string literals over
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comma-separated char literals. This can be a readability and
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compile-time performance win, but upsets some compilers.
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.. option:: -print-enums
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Print enumeration values for a class.
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.. option:: -class=classname
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Make -print-enums print the enumeration list for the specified class.
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.. option:: -print-sets
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Print expanded sets for testing DAG exprs.
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clang-tblgen Options
|
clang-tblgen Options
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~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~
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@ -575,6 +370,234 @@ clang-tblgen Options
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testing purposes.
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testing purposes.
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lldb-tblgen Options
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||||||
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~~~~~~~~~~~~~~~~~~~
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.. option:: gen-lldb-option-defs
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Generate lldb OptionDefinition values.
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.. option:: gen-lldb-property-defs
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Generate lldb PropertyDefinition values.
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.. option:: gen-lldb-property-enum-defs
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Generate lldb PropertyDefinition enum values.
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llvm-tblgen Options
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||||||
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~~~~~~~~~~~~~~~~~~~
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.. option:: -gen-asm-matcher
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Generate assembly instruction matcher.
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.. option:: -match-prefix=prefix
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Make -gen-asm-matcher match only instructions with the given *prefix*.
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.. option:: -gen-asm-parser
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Generate assembly instruction parser.
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.. option:: -asmparsernum=n
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Make -gen-asm-parser emit assembly parser number *n*.
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.. option:: -gen-asm-writer
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Generate assembly writer.
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.. option:: -asmwriternum=n
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Make -gen-asm-writer emit assembly writer number *n*.
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.. option:: -gen-attrs
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Generate attributes.
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.. option:: -gen-automata
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Generate generic automata.
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.. option:: -gen-callingconv
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Generate calling convention descriptions.
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||||||
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||||||
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.. option:: -gen-compress-inst-emitter
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||||||
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||||||
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Generate RISC-V compressed instructions.
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||||||
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||||||
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.. option:: -gen-ctags
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||||||
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||||||
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Generate ctags-compatible index.
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||||||
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.. option:: -gen-dag-isel
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||||||
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||||||
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Generate a DAG (directed acyclic graph) instruction selector.
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||||||
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.. option:: -instrument-coverage
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||||||
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||||||
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Make -gen-dag-isel generate tables to help identify the patterns matched.
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||||||
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||||||
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.. option:: -omit-comments
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||||||
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||||||
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Make -gen-dag-isel omit comments. The default is false.
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||||||
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||||||
|
.. option:: -gen-dfa-packetizer
|
||||||
|
|
||||||
|
Generate DFA Packetizer for VLIW targets.
|
||||||
|
|
||||||
|
.. option:: -gen-directive-decl
|
||||||
|
|
||||||
|
Generate directive related declaration code (header file).
|
||||||
|
|
||||||
|
.. option:: -gen-directive-gen
|
||||||
|
|
||||||
|
Generate directive related implementation code part.
|
||||||
|
|
||||||
|
.. option:: -gen-directive-impl
|
||||||
|
|
||||||
|
Generate directive related implementation code.
|
||||||
|
|
||||||
|
.. option:: -gen-disassembler
|
||||||
|
|
||||||
|
Generate disassembler.
|
||||||
|
|
||||||
|
.. option:: -gen-emitter
|
||||||
|
|
||||||
|
Generate machine code emitter.
|
||||||
|
|
||||||
|
.. option:: -gen-exegesis
|
||||||
|
|
||||||
|
Generate llvm-exegesis tables.
|
||||||
|
|
||||||
|
.. option:: -gen-fast-isel
|
||||||
|
|
||||||
|
Generate a "fast" instruction selector.
|
||||||
|
|
||||||
|
.. option:: -gen-global-isel
|
||||||
|
|
||||||
|
Generate GlobalISel selector.
|
||||||
|
|
||||||
|
.. option:: -gisel-coverage-file=filename
|
||||||
|
|
||||||
|
Specify the file from which to retrieve coverage information.
|
||||||
|
|
||||||
|
.. option:: -instrument-gisel-coverage
|
||||||
|
|
||||||
|
Make -gen-global-isel generate coverage instrumentation.
|
||||||
|
|
||||||
|
.. option:: -optimize-match-table
|
||||||
|
|
||||||
|
Make -gen-global-isel generate an optimized version of the match table.
|
||||||
|
|
||||||
|
.. option:: -warn-on-skipped-patterns
|
||||||
|
|
||||||
|
Make -gen-global-isel explain why a pattern was skipped for inclusion.
|
||||||
|
|
||||||
|
.. option:: -gen-global-isel-combiner
|
||||||
|
|
||||||
|
Generate GlobalISel combiner.
|
||||||
|
|
||||||
|
.. option:: -combiners=list
|
||||||
|
|
||||||
|
Make -gen-global-isel-combiner emit the specified combiners.
|
||||||
|
|
||||||
|
.. option:: -gicombiner-show-expansions
|
||||||
|
|
||||||
|
Make -gen-global-isel-combiner use C++ comments to indicate occurrences
|
||||||
|
of code expansion.
|
||||||
|
|
||||||
|
.. option:: -gicombiner-stop-after-build
|
||||||
|
|
||||||
|
Make -gen-global-isel-combiner stop processing after building the match tree.
|
||||||
|
|
||||||
|
.. option:: -gicombiner-stop-after-parse
|
||||||
|
|
||||||
|
Make -gen-global-isel-combiner stop processing after parsing rules
|
||||||
|
and dump state.
|
||||||
|
|
||||||
|
.. option:: -gen-instr-info
|
||||||
|
|
||||||
|
Generate instruction descriptions.
|
||||||
|
|
||||||
|
.. option:: -gen-instr-docs
|
||||||
|
|
||||||
|
Generate instruction documentation.
|
||||||
|
|
||||||
|
.. option:: -gen-intrinsic-enums
|
||||||
|
|
||||||
|
Generate intrinsic enums.
|
||||||
|
|
||||||
|
.. option:: -intrinsic-prefix=prefix
|
||||||
|
|
||||||
|
Make -gen-intrinsic-enums generate intrinsics with this target *prefix*.
|
||||||
|
|
||||||
|
.. option:: -gen-intrinsic-impl
|
||||||
|
|
||||||
|
Generate intrinsic information.
|
||||||
|
|
||||||
|
.. option:: -gen-opt-parser-defs
|
||||||
|
|
||||||
|
Generate options definitions.
|
||||||
|
|
||||||
|
.. option:: -gen-opt-rst
|
||||||
|
|
||||||
|
Generate option RST.
|
||||||
|
|
||||||
|
.. option:: -gen-pseudo-lowering
|
||||||
|
|
||||||
|
Generate pseudo instruction lowering.
|
||||||
|
|
||||||
|
.. option:: -gen-register-bank
|
||||||
|
|
||||||
|
Generate register bank descriptions.
|
||||||
|
|
||||||
|
.. option:: -gen-register-info
|
||||||
|
|
||||||
|
Generate registers and register classes info.
|
||||||
|
|
||||||
|
.. option:: -register-info-debug
|
||||||
|
|
||||||
|
Make -gen-register-info dump register information for debugging.
|
||||||
|
|
||||||
|
.. option:: -gen-searchable-tables
|
||||||
|
|
||||||
|
Generate generic searchable tables. See :doc:`TableGen BackEnds <../TableGen/BackEnds>`
|
||||||
|
for a detailed description.
|
||||||
|
|
||||||
|
.. option:: -gen-subtarget
|
||||||
|
|
||||||
|
Generate subtarget enumerations.
|
||||||
|
|
||||||
|
.. option:: -gen-x86-EVEX2VEX-tables
|
||||||
|
|
||||||
|
Generate X86 EVEX to VEX compress tables.
|
||||||
|
|
||||||
|
.. option:: -gen-x86-fold-tables
|
||||||
|
|
||||||
|
Generate X86 fold tables.
|
||||||
|
|
||||||
|
.. option:: -long-string-literals
|
||||||
|
|
||||||
|
When emitting large string tables, prefer string literals over
|
||||||
|
comma-separated char literals. This can be a readability and
|
||||||
|
compile-time performance win, but upsets some compilers.
|
||||||
|
|
||||||
|
.. option:: -print-enums
|
||||||
|
|
||||||
|
Print enumeration values for a class.
|
||||||
|
|
||||||
|
.. option:: -class=classname
|
||||||
|
|
||||||
|
Make -print-enums print the enumeration list for the specified class.
|
||||||
|
|
||||||
|
.. option:: -print-sets
|
||||||
|
|
||||||
|
Print expanded sets for testing DAG exprs.
|
||||||
|
|
||||||
|
|
||||||
mlir-tblgen Options
|
mlir-tblgen Options
|
||||||
~~~~~~~~~~~~~~~~~~~
|
~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
@ -718,5 +741,5 @@ mlir-tblgen Options
|
||||||
EXIT STATUS
|
EXIT STATUS
|
||||||
-----------
|
-----------
|
||||||
|
|
||||||
If :program:`xxx-tblgen` succeeds, it will exit with 0. Otherwise, if an error
|
If :program:`*-tblgen` succeeds, it will exit with 0. Otherwise, if an error
|
||||||
occurs, it will exit with a non-zero value.
|
occurs, it will exit with a non-zero value.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue