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[RISCV] Remove unneeded indexed segment load/store vector pseudo instruction. 

We had more combinations of data and index lmuls than we needed.

Also add some asserts to verify that the IndexVT and data VT have
the same element count when we isel these pseudo instructions.
This commit is contained in:
Craig Topper 2021-02-19 10:28:45 -08:00
parent d056d5decf
commit 7f5b3886e4
2 changed files with 50 additions and 26 deletions
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6
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View File

@ -297,6 +297,9 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
"Element count mismatch");
RISCVVLMUL IndexLMUL = getLMUL(IndexVT); RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(
@ -376,6 +379,9 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
"Element count mismatch");
RISCVVLMUL IndexLMUL = getLMUL(IndexVT); RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo( const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(

46
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
View File

@ -2004,19 +2004,28 @@ multiclass VPseudoSSegLoad {
} }
multiclass VPseudoISegLoad<bit Ordered> { multiclass VPseudoISegLoad<bit Ordered> {
foreach idx_eew = EEWList in { // EEW for index argument. foreach idx_eew = EEWList in {
foreach idx_lmul = MxSet<idx_eew>.m in { // LMUL for index argument. foreach sew = EEWList in {
foreach val_lmul = MxList.m in { // LMUL for the value. foreach val_lmul = MxSet<sew>.m in {
defvar IdxLInfo = idx_lmul.MX; defvar octuple_lmul = octuple_from_str<val_lmul.MX>.ret;
defvar IdxVreg = idx_lmul.vrclass; // Calculate emul = eew * lmul / sew
defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), shift_amount<sew>.val);
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar ValLInfo = val_lmul.MX; defvar ValLInfo = val_lmul.MX;
defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = val_lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
let VLMul = val_lmul.value in { let VLMul = val_lmul.value in {
foreach nf = NFSet<val_lmul>.L in { foreach nf = NFSet<val_lmul>.L in {
defvar ValVreg = SegRegClass<val_lmul, nf>.RC; defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo : def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value, nf, Ordered>; VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>;
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" : def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
VPseudoISegLoadMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value, nf, Ordered>; VPseudoISegLoadMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>;
}
} }
} }
} }
@ -2055,19 +2064,28 @@ multiclass VPseudoSSegStore {
} }
multiclass VPseudoISegStore<bit Ordered> { multiclass VPseudoISegStore<bit Ordered> {
foreach idx_eew = EEWList in { // EEW for index argument. foreach idx_eew = EEWList in {
foreach idx_lmul = MxSet<idx_eew>.m in { // LMUL for index argument. foreach sew = EEWList in {
foreach val_lmul = MxList.m in { // LMUL for the value. foreach val_lmul = MxSet<sew>.m in {
defvar IdxLInfo = idx_lmul.MX; defvar octuple_lmul = octuple_from_str<val_lmul.MX>.ret;
defvar IdxVreg = idx_lmul.vrclass; // Calculate emul = eew * lmul / sew
defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), shift_amount<sew>.val);
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar ValLInfo = val_lmul.MX; defvar ValLInfo = val_lmul.MX;
defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
defvar Vreg = val_lmul.vrclass;
defvar IdxVreg = idx_lmul.vrclass;
let VLMul = val_lmul.value in { let VLMul = val_lmul.value in {
foreach nf = NFSet<val_lmul>.L in { foreach nf = NFSet<val_lmul>.L in {
defvar ValVreg = SegRegClass<val_lmul, nf>.RC; defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo : def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value, nf, Ordered>; VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>;
def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" : def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
VPseudoISegStoreMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value, nf, Ordered>; VPseudoISegStoreMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
nf, Ordered>;
}
} }
} }
} }