forked from OSchip/llvm-project
[MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
NarrowScalar G_ZEXTLOAD and G_SEXTLOAD to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66205 llvm-svn: 369512
This commit is contained in:
Petar Avramovic
parent
e406aa791c
commit
7f581df649
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@ -50,9 +50,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.legalFor({{s64, s32}});
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getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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.minScalar(0, s32);
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
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.legalIf([](const LegalityQuery &Query) { return false; })
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@ -6,10 +6,12 @@
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define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
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...
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---
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@ -93,6 +95,32 @@ body: |
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_zextLoad4_s64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[C]](s32)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: load1_s8_to_sextLoad1_s32
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@ -176,3 +204,32 @@ body: |
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_sextLoad4_s64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
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; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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@ -49,6 +49,19 @@ entry:
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ret i16 %conv
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}
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define i64 @load4_s32_to_zextLoad4_s64(i32* %px) {
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; MIPS32-LABEL: load4_s32_to_zextLoad4_s64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lw $2, 0($4)
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; MIPS32-NEXT: ori $3, $zero, 0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = load i32, i32* %px
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%conv = zext i32 %0 to i64
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ret i64 %conv
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}
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define i32 @load1_s8_to_sextLoad1_s32(i8* %px) {
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; MIPS32-LABEL: load1_s8_to_sextLoad1_s32:
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; MIPS32: # %bb.0: # %entry
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@ -96,3 +109,18 @@ entry:
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%conv = sext i8 %0 to i16
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ret i16 %conv
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}
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define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
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; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lw $1, 0($4)
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; MIPS32-NEXT: ori $2, $zero, 31
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; MIPS32-NEXT: srav $3, $1, $2
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; MIPS32-NEXT: move $2, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = load i32, i32* %px
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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@ -6,10 +6,12 @@
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define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
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...
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---
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@ -98,6 +100,31 @@ body: |
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_zextLoad4_s64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%2:_(s64) = G_ZEXT %1(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: load1_s8_to_sextLoad1_s32
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@ -186,3 +213,28 @@ body: |
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_sextLoad4_s64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%2:_(s64) = G_SEXT %1(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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@ -4,8 +4,10 @@
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define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
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define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
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define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
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...
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---
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@ -49,6 +51,33 @@ body: |
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_zextLoad4_s64
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; MIPS32: $v0 = COPY [[LOAD]](s32)
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; MIPS32: $v1 = COPY [[C]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%6:_(s32) = G_CONSTANT i32 0
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%2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: load1_s8_to_sextLoad1_s32
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@ -92,3 +121,37 @@ body: |
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_sextLoad4_s64
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
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; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
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; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
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; MIPS32: $v0 = COPY [[LOAD]](s32)
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; MIPS32: $v1 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%9:_(s32) = G_CONSTANT i32 31
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%10:_(s32) = G_CONSTANT i32 0
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%8:_(s32) = COPY %9(s32)
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%7:_(s32) = G_ASHR %5, %8(s32)
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%2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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